Patents by Inventor Toshiharu Muramatsu

Toshiharu Muramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7248092
    Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: July 24, 2007
    Assignee: DENSO CORPORATION
    Inventors: Katsutoyo Misawa, Yasuyuki Ishikawa, Akira Suzuki, Yoshinori Teshima, Hideaki Ishihara, Toshiharu Muramatsu
  • Publication number: 20050206429
    Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 22, 2005
    Inventors: Katsutoyo Misawa, Yasuyuki Ishikawa, Akira Suzuki, Yoshinori Teshima, Hideaki Ishihara, Toshiharu Muramatsu
  • Patent number: 5940463
    Abstract: An in-vessel structure for a top-entry type fast reactor wherein a core is positioned in the interior of a reactor vessel, an upper core structure being provided above the core, a coolant passing through a cold leg piping inserted from an upper portion of the reactor vessel thereinto and reaching the core, in which the coolant is heated, the coolant then flowing out to an upper plenum, the resultant coolant passing through a hot leg piping, which is inserted from an upper portion of the reaction vessel thereinto, and reaching the outside of the reactor vessel. A plurality of annular fins are fixed horizontally in an axially spaced manner to both the portions of an outer circumferential surface of the upper core structure and the opposite portions of an inner circumferential surface of the reactor vessel, these portions being under the free liquid surface during a rated operation of the reactor.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: August 17, 1999
    Assignee: Japan Nuclear Cycle Development Institute
    Inventor: Toshiharu Muramatsu
  • Patent number: 5699284
    Abstract: A design method for structures is invented, taking into account the effects of fluid temperature fluctuations, comprising: numerical calculations of time-averaged solutions for the motion equation and energy equation for fluids; a Process 1 in which the low-cycle components of the temperature fluctuations occurring on the surface of a tentatively designed structure are analyzed; a Process 2 in which an artificial high-cycle component is superimposed on the low-cycle component of the temperature fluctuations; numerical calculations of accurate solutions for the motion equation and the energy equation for fluids, with the new temperature fluctuations obtained from Process 2 serving as boundary conditions; and a Process 3 in which the high-cycle components of temperature fluctuations occurring at structure surfaces are analyzed. Process 1 and Process 3 are performed by a numerical calculation apparatus equipped with a control section to control time step sizes.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: December 16, 1997
    Assignee: Doryokuro Kakunenryo Kaihatsu Jigyodan
    Inventor: Toshiharu Muramatsu