Patents by Inventor Toshiharu Okada

Toshiharu Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230168811
    Abstract: A semiconductor storage device includes: a data writing unit that writes information data to each block of a memory device in accordance with a write command; a verification processing unit that reads the information data out of a destination block every time after the information data is written to that block, and detects the number of error bits in the read-out information data from each block; and a re-writing unit that writes the information data to a block differing from the destination block if the number of error bits exceeds a prescribed threshold.
    Type: Application
    Filed: November 16, 2022
    Publication date: June 1, 2023
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Toshiharu OKADA
  • Patent number: 11106555
    Abstract: A semiconductor memory device has a memory cell array area including a normal area including memory blocks and a redundant memory area including a redundant block which is a replacement target of a defective block among memory blocks; a storage unit storing address information indicating a position of the defective block in the normal area and address information indicating a position of the redundant block being the replacement target of the defective block, both being in association with each other as a first information; and an output circuit outputting a data row exhibiting a positional relation between the defective block and a memory block other than the defective block in the normal area based on the first information stored in the storage unit in response to the data read signal.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 31, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Toshiharu Okada
  • Patent number: 10818376
    Abstract: A testing method for a semiconductor memory includes determining which memory blocks are defective based on the number of defective cells in the block. The method includes determining whether the number of defective blocks exceeds a first threshold value and judging the semiconductor memory to be defective if the number of defective blocks is equal to or greater than the first threshold value. The method also includes comparing the number of defective blocks with a second threshold value equal to or less than the first threshold value and repeating the process of measuring and judging of the memory cells and memory blocks until the number of defective blocks is at least equal to the second threshold value, and then managing access to the defective blocks in a different manner from accesses to other blocks.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: October 27, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Toshiharu Okada
  • Publication number: 20200027523
    Abstract: A testing method for a semiconductor memory includes determining which memory blocks are defective based on the number of defective cells in the block. The method includes determining whether the number of defective blocks exceeds a first threshold value and judging the semiconductor memory to be defective if the number of defective blocks is equal to or greater than the first threshold value. The method also includes comparing the number of defective blocks with a second threshold value equal to or less than the first threshold value and repeating the process of measuring and judging of the memory cells and memory blocks until the number of defective blocks is at least equal to the second threshold value, and then managing access to the defective blocks in a different manner from accesses to other blocks.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 23, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Toshiharu OKADA
  • Publication number: 20200026628
    Abstract: A semiconductor memory device has a memory cell array area including a normal area including memory blocks and a redundant memory area including a redundant block which is a replacement target of a defective block among memory blocks; a storage unit storing address information indicating a position of the defective block in the normal area and address information indicating a position of the redundant block being the replacement target of the defective block, both being in association with each other as a first information; and an output circuit outputting a data row exhibiting a positional relation between the defective block and a memory block other than the defective block in the normal area based on the first information stored in the storage unit in response to the data read signal.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 23, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Toshiharu OKADA
  • Publication number: 20180285022
    Abstract: A memory system of the present invention has a controller which, for each of a plurality of management groups each including k pieces of blocks (k is an integer equal to two or greater), produces physical block information correspondingly indicating state information indicative of no good when a no-good block is present within the management group. For each management group associated with the state information indicative of no good, the controller employs, as a reuse block, a block other than the no-good block among the k pieces of the blocks included in the management group, and when the total number of the reuse blocks is k, sets the k pieces of the reuse blocks as a new management group.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 4, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Toshiharu OKADA
  • Patent number: 9754685
    Abstract: A memory device is operative to reset write-in status or read-out status information data in accordance with a reset signal. In response to the reset signal, a memory control device refers to a power-on reset check region in a RAM and determines whether or not the received reset signal is a power-on reset signal that is the reset signal generated firstly after power on. If the reset signal is determined to be the power-on reset signal, a memory check process is executed on respective target pages in each block in the memory. A refresh process is also performed on a block in which the number of error bits detected in the memory check process is more than a threshold value. The memory check process is performed on a different page whenever power is supplied.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: September 5, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Toshiharu Okada
  • Publication number: 20160054924
    Abstract: A memory device is operative to reset write-in status or read-out status information data in accordance with a reset signal. In response to the reset signal, a memory control device refers to a power-on reset check region in a RAM and determines whether or not the received reset signal is a power-on reset signal that is the reset signal generated firstly after power on. If the reset signal is determined to be the power-on reset signal, a memory check process is executed on respective target pages in each block in the memory. A refresh process is also performed on a block in which the number of error bits detected in the memory check process is more than a threshold value. The memory check process is performed on a different page whenever power is supplied.
    Type: Application
    Filed: August 18, 2015
    Publication date: February 25, 2016
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Toshiharu OKADA
  • Patent number: 9231506
    Abstract: A The present invention provides a semiconductor device, an electrical device, and a control signal generation method that enable easy generation of a given control signal even by a comparatively low cost and low processing power microcontroller, whereby a microcontroller of a motor control system includes a PWM device equipped with a PWM setting register. The PWM setting register includes a duty update cycle register, a duty update value register and a duty update-times number register. A PWM generator generates and outputs a PWM signal according to values set in each register of the PWM setting register. The PWM device is capable of generating and outputting a PWM signal automatically with the PWM generator according to setting values set in the PWM setting register, even without an interruption by the software (CPU).
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: January 5, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Koji Hiraki, Toshiharu Okada
  • Publication number: 20140042942
    Abstract: The present invention provides a semiconductor device, an electrical device, and a control signal generation method that enable easy generation of a given control signal even by a comparatively low cost and low processing power microcontroller. Namely, a microcontroller of a motor control system includes a PWM device equipped with a PWM setting register. The PWM setting register includes a duty update cycle register, a duty update value register and a duty update-times number register. A PWM generator generates and outputs a PWM signal according to values set in each register of the PWM setting register. The PWM device is capable of generating and outputting a PWM signal automatically with the PWM generator according to setting values set in the PWM setting register, even without an interruption by the software (CPU).
    Type: Application
    Filed: August 7, 2013
    Publication date: February 13, 2014
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: KOJI HIRAKI, TOSHIHARU OKADA
  • Publication number: 20110219194
    Abstract: A data relaying apparatus and method capable of relaying data in a highly efficient manner. Data of a predetermined read-ahead size is acquired from the storage apparatus from a top address indicated by a data read request to temporarily store the data as temporary storage data and, each time a subsequent data read request is made, data of a transmission data size corresponding to a type of the subsequent data read request is read out sequentially from a top position of the temporary storage data to relay the data to a data processing apparatus.
    Type: Application
    Filed: February 28, 2011
    Publication date: September 8, 2011
    Applicant: OKI SEMICONUCTOR CO., LTD.
    Inventor: Toshiharu Okada
  • Patent number: 7402745
    Abstract: The present invention provides a MIDI playing method comprising the steps of when synchronous event messages embedded in MIDI data are detected on the sequencer side which analyzes MIDI data in order along a time series of the MIDI data where the MIDI data are analyzed from the head of music to carry out MIDI musical performance, accumulating the number of the synchronous event messages and requesting a host CPU to make interrupt processing; and executing synchronous event processing on the host CPU side having received the request for the interrupt processing therein until the number of executed synchronous events and the accumulated value coincide with each other.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: July 22, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshiharu Okada
  • Patent number: 7285711
    Abstract: A music player has sequencers each including a reading and restoring function unit for reading music information including header information, a delta time, and a message and restoring running status of the message; a message analyzing and processing function unit for analyzing the header information, consuming a period of time according to the delta time, and processing the message to generate sound source drive information; a writing function unit for writing the sound source drive information into an output memory; and a sequencer controlling function unit for controlling the reading and restoring function unit to read and restore the music information, controlling the message analyzing and processing function unit to analyze the header information, and controlling the message analyzing and processing function unit and the writing function unit to consume the period of time, generate the sound source drive information, and write the sound source drive information.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: October 23, 2007
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventors: Toshiharu Okada, Kaoru Tsukamoto, Tomohiro Iwanaga, Yoji Hamano
  • Publication number: 20060201314
    Abstract: The present invention provides a MIDI playing method comprising the steps of when synchronous event messages embedded in MIDI data are detected on the sequencer side which analyzes MIDI data in order along a time series of the MIDI data where the MIDI data are analyzed from the head of music to carry out MIDI musical performance, accumulating the number of the synchronous event messages and requesting a host CPU to make interrupt processing; and executing synchronous event processing on the host CPU side having received the request for the interrupt processing therein until the number of executed synchronous events and the accumulated value coincide with each other.
    Type: Application
    Filed: October 31, 2005
    Publication date: September 14, 2006
    Inventor: Toshiharu Okada
  • Publication number: 20060130638
    Abstract: A music player has sequencers each including a reading and restoring function unit for reading music information including header information, a delta time, and a message and restoring running status of the message; a message analyzing and processing function unit for analyzing the header information, consuming a period of time according to the delta time, and processing the message to generate sound source drive information; a writing function unit for writing the sound source drive information into an output memory; and a sequencer controlling function unit for controlling the reading and restoring function unit to read and restore the music information, controlling the message analyzing and processing function unit to analyze the header information, and controlling the message analyzing and processing function unit and the writing function unit to consume the period of time, generate the sound source drive information, and write the sound source drive information.
    Type: Application
    Filed: August 17, 2005
    Publication date: June 22, 2006
    Inventors: Toshiharu Okada, Kaoru Tsukamoto, Tomohiro Iwanaga, Yoji Hamano
  • Patent number: 6946091
    Abstract: When drilling a multi layered sheet-like material, drilling is first made with pulses having energy that generates an inter-layer pull-off force smaller than the adhesion force between the layers. Then pulses with higher energy are radiated for trimming the shape of the holes, and thus through-holes having a desired shape are drilled without causing delamination of the layers.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: September 20, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Izuru Nakai, Toshiharu Okada, Haruhiro Yuki
  • Publication number: 20040241632
    Abstract: This invention provides karaoke system that reduces declination between playing melody signaling an incoming call and displaying characters or pictures. To this end, the karaoke system of this invention plays karaoke song comprising contents with karaoke event data, and synchronization of karaoke events are achieved by executing the events described in time order in the contents of the karaoke by following a timing dictated by synchronization data.
    Type: Application
    Filed: December 9, 2003
    Publication date: December 2, 2004
    Inventors: Kaoru Tsukamoto, Tomohiro Iwanaga, Toshiharu Okada
  • Patent number: 6770843
    Abstract: In a laser processing apparatus including a laser oscillator for emitting laser light onto a workpiece through an f&thgr; lens for drilling a hole in the workpiece, a wavelength selector for passing only a light ray having a specific wavelength is disposed between the laser oscillator and the workpiece.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: August 3, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Izuru Nakai, Toshiharu Okada, Haruhiro Yuki, Ken Muneyuki
  • Patent number: 6671951
    Abstract: In manufacturing a double-layered or a multi-layered printed wiring board, a layer of metamorphic substance, which is created by transmuting a substrate material, is formed on an inner wall of a hole during a perforation process of the substrate utilizing radiation energy. The layer of metamorphic substance prevents conductive materials constituting electrical connection means formed on the inner wall of the hole from dispersing over a surface of the substrate or permeating into the substrate.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: January 6, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshihiro Nishii, Shigeru Yamane, Shinji Nakamura, Hidenori Hayashi, Toru Fujimoto, Toshiharu Okada, Izuru Nakai
  • Patent number: 6518515
    Abstract: In manufacturing a double-layered or a multi-layered printed wiring board, a layer of metamorphic substance, which is created by transmuting a substrate material, is formed on an inner wall of a hole during a perforation process of the substrate utilizing radiation energy. The layer of metamorphic substance prevents conductive materials constituting electrical connection formed on the inner wall of the hole from dispersing over a surface of the substrate or permeating into the substrate.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: February 11, 2003
    Assignee: Matsushita Electric Industrial Co, Ltd.
    Inventors: Toshihiro Nishii, Shigeru Yamane, Shinji Nakamura, Hidenori Hayashi, Toru Fujimoto, Toshiharu Okada, Izuru Nakai