Patents by Inventor Toshiharu Okamoto
Toshiharu Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9230946Abstract: The present invention provides a multichip package in which a first semiconductor chip having an RF analog circuit area and a digital circuit area, and a second semiconductor chip having a digital circuit area are plane-arranged over an organic multilayer wiring board and coupled to each other by bonding wires. In the multichip package, the first semiconductor chip is made thinner than the second semiconductor chip.Type: GrantFiled: December 13, 2013Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Yoshihiro Masumura, Hideki Sasaki, Toshiharu Okamoto
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Patent number: 9197227Abstract: The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit. The oscillation circuit includes an inverting amplifier and a resistor coupled in parallel to the inverting amplifier. The oscillation circuit in which the inverting amplifier is coupled to a crystal oscillator outside the chip generates an oscillation circuit by driving the crystal oscillator. The effective value measuring circuit measures an effective value of an oscillation signal produced by the oscillation circuit. The control unit controls the gain of the inverting amplifier so that the effective value will be equal to a target voltage.Type: GrantFiled: July 11, 2014Date of Patent: November 24, 2015Assignee: Renesas Electronics CorporationInventor: Toshiharu Okamoto
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Publication number: 20150028956Abstract: The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit. The oscillation circuit includes an inverting amplifier and a resistor coupled in parallel to the inverting amplifier. The oscillation circuit in which the inverting amplifier is coupled to a crystal oscillator outside the chip generates an oscillation circuit by driving the crystal oscillator. The effective value measuring circuit measures an effective value of an oscillation signal produced by the oscillation circuit. The control unit controls the gain of the inverting amplifier so that the effective value will be equal to a target voltage.Type: ApplicationFiled: July 11, 2014Publication date: January 29, 2015Inventor: Toshiharu Okamoto
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Patent number: 8760943Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.Type: GrantFiled: August 30, 2012Date of Patent: June 24, 2014Assignee: Renesas Electronics CorporationInventors: Toshihiko Funaki, Toshiharu Okamoto, Muneaki Matsushige, Kenichi Kuboyama, Shuuichi Senou, Susumu Takano
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Publication number: 20140167292Abstract: The present invention provides a multichip package in which a first semiconductor chip having an RF analog circuit area and a digital circuit area, and a second semiconductor chip having a digital circuit area are plane-arranged over an organic multilayer wiring board and coupled to each other by bonding wires. In the multichip package, the first semiconductor chip is made thinner than the second semiconductor chip.Type: ApplicationFiled: December 13, 2013Publication date: June 19, 2014Applicant: Renesas Electronics CorporationInventors: Yoshihiro MASUMURA, Hideki SASAKI, Toshiharu OKAMOTO
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Publication number: 20130051110Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.Type: ApplicationFiled: August 30, 2012Publication date: February 28, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshihiko FUNAKI, Toshiharu OKAMOTO, Muneaki MATSUSHIGE, Kenichi KUBOYAMA, Shuuichi SENOU, Susumu TAKANO
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Patent number: 8314649Abstract: Provided is a semiconductor apparatus including a divided voltage generation circuit that includes a first resistor element and a first transistor connected in series between a first power supply and a second power supply and generates a divided voltage by dividing a voltage difference between the first power supply and the second power supply with a resistance ratio of the first resistor element and the first transistor specified according to a level of a first current flowing to the first transistor, and a current control circuit that includes a second transistor that is connected in a mirror configuration to the first transistor and determines the level of the first current by a control current flowing from a first terminal to a second terminal, and increases and decreases the control current according to an increase and decrease in a voltage difference between the first power supply and a ground power supply.Type: GrantFiled: August 27, 2012Date of Patent: November 20, 2012Assignee: Renesas Electronics CorporationInventor: Toshiharu Okamoto
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Patent number: 8283969Abstract: Provided is a semiconductor apparatus including a divided voltage generation circuit that includes a first resistor element and a first transistor connected in series between a first power supply and a second power supply and generates a divided voltage by dividing a voltage difference between the first power supply and the second power supply with a resistance ratio of the first resistor element and the first transistor specified according to a level of a first current flowing to the first transistor, and a current control circuit that includes a second transistor that is connected in a mirror configuration to the first transistor and determines the level of the first current by a control current flowing from a first terminal to a second terminal, and increases and decreases the control current according to an increase and decrease in a voltage difference between the first power supply and a ground power supply.Type: GrantFiled: May 5, 2010Date of Patent: October 9, 2012Assignee: Renesas Electronics CorporationInventor: Toshiharu Okamoto
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Publication number: 20100327846Abstract: Provided is a semiconductor apparatus including a divided voltage generation circuit that includes a first resistor element and a first transistor connected in series between a first power supply and a second power supply and generates a divided voltage by dividing a voltage difference between the first power supply and the second power supply with a resistance ratio of the first resistor element and the first transistor specified according to a level of a first current flowing to the first transistor, and a current control circuit that includes a second transistor that is connected in a mirror configuration to the first transistor and determines the level of the first current by a control current flowing from a first terminal to a second terminal, and increases and decreases the control current according to an increase and decrease in a voltage difference between the first power supply and a ground power supply.Type: ApplicationFiled: May 5, 2010Publication date: December 30, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Toshiharu OKAMOTO
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Patent number: 7746161Abstract: A semiconductor device includes a first voltage generator which outputs a first signal to a first node, a second voltage generator which outputs a second signal to a second node, a capacitor coupled between the first and second nodes; and a current supply circuit coupled to said second node. While the first voltage generator outputs the first signal to set the first node to a first voltage potential, the second voltage generator is activated to output the second signal to set the second node to a second voltage potential. At that time, the capacitor influences to the second node, based on a coupling capacitance thereof and the current supplying circuit supplies a current to suppress the influence.Type: GrantFiled: November 13, 2007Date of Patent: June 29, 2010Assignee: NEC Electronics CorporationInventor: Toshiharu Okamoto
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Publication number: 20090295774Abstract: A semiconductor integrated circuit device, includes: a RAM (Random Access Memory) circuit; and an internal power source circuit. The RAM circuit includes a plurality of RAM circuit blocks. The internal power source circuit supplies a voltage a selection RAM block selected from the plurality of RAM circuit blocks, wherein the voltage corresponds to an arrangement place of the selection RAM circuit block.Type: ApplicationFiled: May 26, 2009Publication date: December 3, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Toshiharu Okamoto
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Patent number: 7446594Abstract: Disclosed is a booster circuit comprising a voltage detection circuit for outputting a decision output signal for detecting a boosted voltage and controlling a voltage boosting operation, an oscillation circuit, and a plurality of charge pump circuits. The oscillation circuit includes an odd number of stages of control-type inverters. When the decision output signal from the voltage detection circuit indicates the voltage boosting operation (oscillation), the odd number of stages of inverters constitute a closed path. Oscillation outputs from outputs of the control-type inverters are thereby extracted, respectively. When the decision output signal indicates a stop of the voltage boosting operation (stop of the oscillation), output values of the control-type inverters are not inverted and held, and the oscillation is thereby stopped. The charge pump circuits receive output signals from the control-type inverters as clock signals, respectively, and operate.Type: GrantFiled: August 1, 2006Date of Patent: November 4, 2008Assignee: NEC Electronics CorporationInventors: Kazunori Yamane, Akira Satou, Toshiharu Okamoto
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Publication number: 20080191990Abstract: A driver includes a first memory including a plurality of memory cells and redundant memory cells. An address control circuit replaces a defective memory cell of the plurality of memory cells with one of the redundant memory cells based on a defect address data indicating an address of the defective memory cell. A driving circuit displays on a display panel, a display data stored in the first memory based on a display quality specifying data specifying display quality of the display panel. The display quality specifying data and the defect address data are stored in a second memory.Type: ApplicationFiled: February 6, 2008Publication date: August 14, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroyuki MATSUBARA, Hiroyuki TAKAHASHI, Nobuyuki ORITA, Toshiharu OKAMOTO, Shuuichi SENOU
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Publication number: 20080122527Abstract: A semiconductor device includes a first voltage generator which outputs a first signal to a first node, a second voltage generator which outputs a second signal to a second node, a capacitor coupled between the first and second nodes; and a current supply circuit coupled to said second node. While the first voltage generator outputs the first signal to set the first node to a first voltage potential, the second voltage generator is activated to output the second signal to set the second node to a second voltage potential. At that time, the capacitor influences to the second node, based on a coupling capacitance thereof and the current supplying circuit supplies a current to suppress the influence.Type: ApplicationFiled: November 13, 2007Publication date: May 29, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Toshiharu Okamoto
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Patent number: 7274248Abstract: A booster circuit for boosting an externally supplied voltage includes a plurality of parallel-connected charge pump units. The charge pump units are activated successively in accordance with a boosted voltage to suppress peak current at start-up of the booster circuit and reduce fluctuation of power supply voltage.Type: GrantFiled: March 4, 2005Date of Patent: September 25, 2007Assignee: NEC Electronics CorporationInventor: Toshiharu Okamoto
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Publication number: 20070030082Abstract: Disclosed is a booster circuit comprising a voltage detection circuit for outputting a decision output signal for detecting a boosted voltage and controlling a voltage boosting operation, an oscillation circuit, and a plurality of charge pump circuits. The oscillation circuit includes an odd number of stages of control-type inverters. When the decision output signal from the voltage detection circuit indicates the voltage boosting operation (oscillation), the odd number of stages of inverters constitute a closed path. Oscillation outputs from outputs of the control-type inverters are thereby extracted, respectively. When the decision output signal indicates a stop of the voltage boosting operation (stop of the oscillation), output values of the control-type inverters are not inverted and held, and the oscillation is thereby stopped. The charge pump circuits receive output signals from the control-type inverters as clock signals, respectively, and operate.Type: ApplicationFiled: August 1, 2006Publication date: February 8, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Kazunori Yamane, Akira Satou, Toshiharu Okamoto
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Publication number: 20050195019Abstract: A booster circuit for boosting an externally supplied voltage includes a plurality of parallel-connected charge pump units. The charge pump units are activated successively in accordance with a boosted voltage to suppress peak current at start-up of the booster circuit and reduce fluctuation of power supply voltage.Type: ApplicationFiled: March 4, 2005Publication date: September 8, 2005Applicant: NEC ELECTRONICS CORPORATIONInventor: Toshiharu Okamoto
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Publication number: 20040146771Abstract: Disclosed are a method of producing a fuel cell separator. In this method, dry granules of a composition for a fuel cell separator mainly containing a conductive material, a binder, and an additive are produced by mixing raw materials including at least the conductive material, the binder, and the additive, granulating the resultant mixture to obtain granules, and drying the granules. The dry granules may be further sized. Then, the granules are packed in a mold, and hot-press molded. This method is characterized in that the granules have a residual volatile matter content in a range of 4 wt % or less, and an average particle size in a range of 200 to 700 &mgr;m (60 to 160 &mgr;m for the sized granules) and a specific particle size distribution. With this method, a fuel cell separator having a high elasticity, an excellent dimensional accuracy, and a high gas non-permeability can be produced with no molding failures, accordingly, with a uniform quality.Type: ApplicationFiled: January 16, 2004Publication date: July 29, 2004Applicant: Nisshinbo Industries, Inc.Inventors: Kazuo Saito, Toshiharu Okamoto, Atsushi Hagiwara, Ayumi Horiuchi
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Patent number: 6764624Abstract: A method of producing a fuel cell separator in which dry granules of a composition for a fuel cell separator mainly containing a conductive material, a binder, and an additive are produced by mixing raw materials including at least the conductive material, the binder, and the additive, granulating the resultant mixture to obtain granules, and drying the granules. The dry granules may be further sized. Then the granules are packed in a mold and hot-press molded. The granules have a residual volatile matter content in a range of 4 weight-% or less, and an average particle size in a range of 200 to 700 &mgr;m (60 to 160 &mgr;m for the sized granules) and a specific particle size distribution.Type: GrantFiled: May 15, 2001Date of Patent: July 20, 2004Assignee: Nisshinbo Industries, Inc.Inventors: Kazuo Saito, Toshiharu Okamoto, Atsushi Hagiwara, Ayumi Horiuchi
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Patent number: 6601003Abstract: A voltage-divided voltage from a power supply voltage-dividing circuit is compared at a comparison circuit with a reference voltage from a reference voltage generation circuit. A low power-supply voltage signal is output, this signal being ON if the voltage-divided voltage is lower than the reference voltage, and OFF if the voltage-divided voltage is greater than the reference voltage. A low power-supply voltage control circuit receives the low power-supply voltage signal and, when the low power-supply voltage signal switches from OFF to ON, either suspends or executes an operation of switching a memory control signal that is output to the nonvolatile memory from active to inactive. This switching operation is halted at times such as when a power-supply voltage drop of extremely short time interval is expected.Type: GrantFiled: March 12, 2001Date of Patent: July 29, 2003Assignee: NEC Electronics CorporationInventor: Toshiharu Okamoto