Abstract: A shift register latch (SRL) (300, 304, 400) compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (64). The SRL includes a master latch (308, 308?, 404), a slave latch (312, 312?, 408) and a circuit element (328, 328?, 416) connected between the scan clock tree and the master latch. The scan clock generates a clock signal (350, 440) having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (354, 354?) based on the scan clock signal for triggering the master latch.

Abstract: A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Abstract: A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the memory array based on results of the first set of tests; and shmoo testing the memory array by incrementing, decrementing or incrementing and decrementing values of a test parameter until a minimum or maximum value of the test parameter is reached that utilizes a second number of the total number of fuses for use in repairing the memory array to operate at the minimum or maximum value of the test parameter.

Abstract: A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.

Abstract: A shift register latch (SRL) (300, 304, 400) compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (64). The SRL includes a master latch (308, 308?, 404), a slave latch (312, 312?, 408) and a circuit element (328, 328?, 416) connected between the scan clock tree and the master latch. The scan clock generates a clock signal (350, 440) having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (354, 354?) based on the scan clock signal for triggering the master latch.

Abstract: A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the memory array based on results of the first set of tests; and shmoo testing the memory array by incrementing, decrementing or incrementing and decrementing values of a test parameter until a minimum or maximum value of the test parameter is reached that utilizes a second number of the total number of fuses for use in repairing the memory array to operate at the minimum or maximum value of the test parameter.

Abstract: A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Abstract: An apparatus and method for blowing fuses in an integrated circuit. The apparatus and method use a plurality of fuse blowing circuits coupled serially. Each successive fuse blowing circuit is activated by an activate signal generated by a previous fuse blowing circuit. The apparatus and method provide for the fuse blowing operation to be both self-timing and self-testing.

Abstract: A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Abstract: An apparatus and method for blowing fuses in an integrated circuit. The apparatus and method use a plurality of fuse blowing circuits coupled serially. Each successive fuse blowing circuit is activated by an activate signal generated by a previous fuse blowing circuit. The apparatus and method provide for the fuse blowing operation to be both self-timing and self-testing.

Abstract: The present invention provides a method and device for reduced-pin integrated circuit I/O testing. In this regard, the present invention provides for the testing of an integrated circuit or chip in a manner which is independent of the number of test pins present on the testing device. The method and device of the present invention are realized through an integrated circuit having two test ports: a scannable I/O test port and a Forcing-Measuring test port, and a plurality of switches. The scannable I/O test port is employed for the input and output of, among other things, scannable shift-register latch data which affects the states of the plurality of switches in the integrated circuit. The Forcing-Measuring test port is employed for, among other things, forcing or measuring voltages and currents associated with the I/O circuits under test through the switches to the circuits under test.

Abstract: This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.

Abstract: A method and apparatus for testing or verifying proper operation of a data output system of a memory system are provided. A known data signal is applied to a bit line, independent of the memory cells of the memory system associated with the bit line. Expected outputs of the data output system are determined based upon the formation or configuration of the data output system and the known data signal. Following application of the known data signal to the bit line, actual outputs of the data output system are compared to the expected outputs to verify proper operation of the data output system.

Abstract: A method and apparatus for testing or verifying proper operation of an address system of a memory system are provided. The address system includes a write unit for driving write word lines, based on a write address, and a read unit for driving read word lines, based on a read address. A common address is applied to the write unit and read unit, and the outputs thereof are compared for equivalency, using a verification circuit. Proper operation of the address system is indicated by the verification circuit if the outputs of the write and read units are equivalent, and improper operation is indicated if the outputs are not equivalent.

Abstract: A disc-shaped diaphragm 16 is fixed on a protruding portion 15a formed on the bottom of case 15. Piezoelectric elements 17 and 18 are bonded on upper and lower surfaces of the diaphragm 16. A printed circuit board 24 closes the opening of case 15. Outer surfaces of case 15 and printed circuit board 24 are covered by a resin package 28. Lead terminals 22 and 23 are held by a lead holding member 21. Lend terminals 22 and 23 connect the piezoelectric elements 17 and 18 with a circuit on printed circuit board 24. With this arrangement, it becomes possible to provide an acceleration sensor used in an air bag system which is capable of reducing the number of parts and simplifying the structure.