Patents by Inventor Toshiharu Sakurai
Toshiharu Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5198883Abstract: First and second frame bodies are used to fabricate a semiconductor device. The first frame body includes a die pad. The second frame body only includes a plurality of leads. The die pad is depressed by a predetermined amount which is equal or greater than the thickness of a semiconductor chip to be mounted on the die pad. The two frame bodies are welded, and wire bonding and cutting of the leads are performed.Type: GrantFiled: July 19, 1989Date of Patent: March 30, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Takahashi, Yasuhiro Yamaji, Susumu Harada, Kazuichi Komenaka, Mitsugu Miyamoto, Masashi Muromachi, Hiroshi Harada, Kazuo Numajiri, Haruyuki Shimakawa, Toshiharu Sakurai
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Patent number: 5175005Abstract: A method of controlling tumor cell metastasis comprising administering to a human a therapeutically effective amount of a ribonuclease inhibitor.Type: GrantFiled: October 2, 1989Date of Patent: December 29, 1992Assignee: Morinaga & Co., Ltd.Inventors: Koji Fukushima, Tsutomu Honjo, Tomonobu Fujita, Haruhisa Fujita, Toshiharu Sakurai
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Patent number: 5096081Abstract: A metal cover plate for covering a semiconductor chip mounted on a package base plate comprises an upper central portion, a flange extending outwardly from outer edges of the central portion, and a side wall portion extending perpendicularly from the flange along all sides thereof. The central portion has at least one portion in parallel with the package base plate. The central portion is formed with reinforcing portions in the form ridges of gable roofs and valleys in cross section, formed along diagonal lines of the central portion or in the form of a ridge or rib substantially semicircular in cross section extending upwardly or downwardly along each diagonal line. Deflection of the top wall portion of the package during pressure application is thus be minimized.Type: GrantFiled: February 22, 1989Date of Patent: March 17, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Masamichi Shindo, Toshiharu Sakurai, Hideo Taguchi, Nobu Izawa
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Patent number: 5091341Abstract: A method of sealing a semiconductor device with resin includes the steps of coupling the tie bar of a lead frame to a heat sink; die bonding a semiconductor chip to the surface of the heat sink; wire bonding and electrically connecting the semiconductor chip to leads of the lead frame; placing the heat sink on the bottom surface of a cavity of a lower mold, putting an upper mold on the lower mold, and pressing down the coupling portion between the heat sink and lead frame toward the bottom surface by using a pressure member mounted on the upper mold; and injecting melted resin within the cavity defined by the upper and lower molds, and hardening the resin.Type: GrantFiled: May 17, 1990Date of Patent: February 25, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Asada, Kenji Takahashi, Toshiharu Sakurai
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Patent number: 5025347Abstract: A semiconductor device of a type having a pin grid array, comprises a printed circuit board and a planar metal stem with a plurality of through holes. The stem is made of metal having a coefficient of thermal expansion .alpha.s. The printed circuit board has a predetermined wiring pattern on its upper surface and is made of a material having a maximum coefficient .alpha.p in the widthwise direction. The printed circuit board is superposed over the upper surface of the metal stem. A plurality of lead pins have upper portions inserted into the through holes of the stem and board and are in alignment with each other when the board and the stem are superposed one upon another. Connecting members connect the upper portions of the lead pins with their corresponding wiring patterns. In the semiconductor device, the absolute value .DELTA..alpha. of the difference between the maximum coefficient .alpha.p of the board and the coefficient .alpha.s of the stem (.DELTA..alpha.=.alpha.p -.alpha.Type: GrantFiled: April 11, 1989Date of Patent: June 18, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Masamichi Shindo, Toshiharu Sakurai, Hideo Taguchi, Nobu Izawa
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Patent number: 4910577Abstract: In a lead frame having a number of square dimples arranged on the rear side of a bed portion in a lattice form of a pitch t, each side of the square dimples is disposed to form a predetermined angle relative to either of X--Y axes of the lattice extending in lateral and longitudinal directions of the bed portion. The square dimples may be provided at entire intersecting points between two sets of lines extending in parallel with the X and Y axes, or every other intersecting points of the same, so that an equal pitch of t or 2t is maintained between the dimples arranged in X and Y directions.Type: GrantFiled: August 8, 1988Date of Patent: March 20, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Sonoda, Toshiharu Sakurai, Akinori Nakatsuru, Tetsuo Ito
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Patent number: 4855807Abstract: This invention provides a semiconductor device comprising a die-pad supported by tie-bars, a semiconductor element mounted on the die-pad with the die-pad, tie-bars and semiconductor element being encapsulated in a moulding compound, means for defining an aperture which extends in to the moulding compound so as to expose a portion of a tie-bar.Type: GrantFiled: December 18, 1987Date of Patent: August 8, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Yamaji, Kenji Takahashi, Seiichi Hirata, Toshiharu Sakurai
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Patent number: 4654692Abstract: Slits are formed in the metal wiring layer formed on the semiconductor of a semiconductor device to be resin sealed thereby to divide the total width of the metal wiring layer into divided widths each of the order of 30 to 40 .mu.m, whereby stress generated in the metal wiring layer is absorbed and prevented from causing cracking, deformation, and other defects. The slits are arranged to be substantially parallel to the peripheral side of the device which is most closely located to the wiring part.Type: GrantFiled: August 6, 1986Date of Patent: March 31, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Toshiharu Sakurai, Seiichi Hirata
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Patent number: 4604642Abstract: What is disclosed is a semiconductor apparatus comprises a semiconductor element, a pair of in-line electrode leads having a mounting island supporting the semiconductor element and a molded housing of resin compound. The electrode leads and mounting island are made of an alloy having a thermal expansion coefficient in the range of about 7.times.10.sup.-6 1/C.degree. to about 14.times.10.sup.-6 1/C.degree.. Thus, when the device is subjected to temperature variations, there is little warpage or cracking in the device.Type: GrantFiled: March 26, 1984Date of Patent: August 5, 1986Assignee: Kabushiki Kaisha ToshibaInventor: Toshiharu Sakurai
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Patent number: 4482611Abstract: An electronic part composed of an alloy comprising, as a basic metal or metals, Cr and Zr with the total amount thereof being between 0.3 and 2.0% by weight (provided that the amount of Cr is 1.5% by weight or less and that of Zr is 1.0% by weight or less) and Cu as a balance, the surface of said part having been coated with Sn.The electronic part according to the present invention is excellent in the wetting property of a solder, weather resistance of a solder and bonding property to Au and Al.Type: GrantFiled: December 20, 1982Date of Patent: November 13, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Koichi Teshima, Masakazu Yamada, Toshiharu Sakurai, Takemi Abe