Abstract: There is provided a reference voltage generating circuit including: a first PN junction element (PN1) whose forward voltage is a first voltage V1; a second PN junction element (PN2) having a current density different from the first PN junction element and whose forward voltage is a second voltage V2 higher than the first voltage V1; and generating circuits (101 to 103) inputting the first voltage V1 and the second voltage V2 and generating a reference voltage expressed by A2×V2+A3×(A2×V2?A1×V1) in which A1, A2, and A3 are set to be coefficients, and in which A1 and A2 are different values.

Abstract: There is provided a reference voltage generating circuit including: a first PN junction element (PN1) whose forward voltage is a first voltage V1; a second PN junction element (PN2) having a current density different from the first PN junction element and whose forward voltage is a second voltage V2 higher than the first voltage V1; and generating circuits (101 to 103) inputting the first voltage V1 and the second voltage V2 and generating a reference voltage expressed by A2×V2+A3×(A2×V2?A1×V1) in which A1, A2, and A3 are set to be coefficients, and in which A1 and A2 are different values.

Abstract: A semiconductor device has transistors (P1,P10,P11) formed in an active region (22) isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P10,P11) that require symmetry or relativity characteristics, wherein the distances (S1) between a gate electrode and one end of the active region on a source side viewed from the gate electrode in the first and second transistor are substantially same, and the distances (D1) between a gate electrode and one end of the active region on a drain side viewed from the gate electrode in the first and second transistor are substantially same. The predetermined circuit includes, for example, a current mirror circuit that has a transistor pair of which gate is commonly connected, and a differential circuit that has a transistor pair whose sources are commonly connected, where an input signal is supplied to the gate, and an output signal is generated in the drain.

Abstract: A semiconductor device has transistors (P1,P10,P11) formed in an active region (22) isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P10,P11) that require symmetry or relativity characteristics, wherein the distances (S1) between a gate electrode and one end of the active region on a source side viewed from the gate electrode in the first and second transistor are substantially same, and the distances (D1) between a gate electrode and one end of the active region on a drain side viewed from the gate electrode in the first and second transistor are substantially same. The predetermined circuit includes, for example, a current mirror circuit that has a transistor pair of which gate is commonly connected, and a differential circuit that has a transistor pair whose sources are commonly connected, where an input signal is supplied to the gate, and an output signal is generated in the drain.

Abstract: The capacitor comprises a lower layer electrode 22 formed on a substrate 10 with an inter-layer insulation film 12 therebetween; an upper layer electrode 24 opposed to the lower layer electrode 22 with an inter-layer insulation film 12 therebetween, a lower interconnection layer 14 formed between the substrate 10 and the lower layer electrode 22, and electrically connected to the upper layer electrode 24, whereby the parasitic capacitance, which is a cause for lower capacitor accuracy, useless power consumption, etc. can be drastically decreased, and external noises can be shielded off.

Abstract: The capacitor comprises a lower layer electrode 22 formed on a substrate 10 with an inter-layer insulation film 12 therebetween; an upper layer electrode 24 opposed to the lower layer electrode 22 with an inter-layer insulation film 12 therebetween, a lower interconnection layer 14 formed between the substrate 10 and the lower layer electrode 22, and electrically connected to the upper layer electrode 24, whereby the parasitic capacitance, which is a cause for lower capacitor accuracy, useless power consumption, etc. can be drastically decreased, and external noises can be shielded off.