Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.

Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.

Abstract: A semiconductor device whose insertion loss is reduced and isolation characteristics are improved in a high frequency band by reducing the capacitance component when an FET is off is provided. FETs (30a, 30b) having a gate electrode with a gate length of not more than 0.8 ?m are formed on a semiconductor substrate in which a buffer layer (24) having an impurity concentration of at least 1010 cm?3 and at most 1014 cm?3 is formed on a semi-insulating semiconductor (25) having at least 1014 cm?3 and at most 1016 cm?3 p-type or n-type impurities and an active layer (23) having a p-type or n-type impurity concentration of at least 1015 cm?3 and at most 1017 cm?3 is formed on the buffer layer.

Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.

Abstract: A semiconductor device whose insertion loss is reduced and isolation characteristics are improved in a high frequency band by reducing the capacitance component when an FET is off is provided. FETs (30a, 30b) having a gate electrode with a gate length of not more than 0.8 &mgr;m are formed on a semiconductor substrate in which a buffer layer (24) having an impurity concentration of at least 1010 cm−3 and at most 1014 cm−3 is formed on a semi-insulating semiconductor (25) having at least 1014 cm−3 and at most 1016 cm−3 p-type or n-type impurities and an active layer (23) having a p-type or n-type impurity concentration of at least 1015 cm−3 and at most 1017 cm−3 is formed on the buffer layer.

Abstract: This invention relates to a method of manufacturing an Arsenic-including compound semiconductor device comprising the steps of forming an ion implantation layer in a specified region of an As compound semiconductor wafer, forming an As layer on the surface of the wafer, and annealing the water. In this manner, As evaporation in the ion implantation layer by annealing heat may be prevented. Accordingly, sufficient substitution of the implanted ions and the ions other than As ions composing the As compound may be achieved, thereby preventing lowering of the electrical activation of the As compound semiconductor device. In addition, the electrical activation becomes uniform over the whole area of the water.