Patents by Inventor Toshiharu Tanbo

Toshiharu Tanbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor element and method for fabricating the same
    Patent number: 7176098
    Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a second semiconductor layer formed on a predetermined part of the first semiconductor layer. An inactivated region is formed, by ion implantation, in a region of the collector layer located below the base layer except for a part thereof corresponding to the second semiconductor layer. The edge of the inactivated region is located away from the edge of the second semiconductor layer, and a region of the first semiconductor layer between the edge of the inactivated region and the edge of the second semiconductor layer is depleted.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keisuke Kojima, Toshiharu Tanbo, Keiichi Murayama
  • Semiconductor element and method for fabricating the same
    Publication number: 20050199911
    Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a second semiconductor layer formed on a predetermined part of the first semiconductor layer. An inactivated region is formed, by ion implantation, in a region of the collector layer located below the base layer except for a part thereof corresponding to the second semiconductor layer. The edge of the inactivated region is located away from the edge of the second semiconductor layer, and a region of the first semiconductor layer between the edge of the inactivated region and the edge of the second semiconductor layer is depleted.
    Type: Application
    Filed: February 23, 2005
    Publication date: September 15, 2005
    Inventors: Keisuke Kojima, Toshiharu Tanbo, Keiichi Murayama