Patents by Inventor Toshiharu Yubitani

Toshiharu Yubitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7374614
    Abstract: The method for manufacturing a single crystal semiconductor achieves an object to reduce the impurity concentration nonuniformity within a semiconductor wafer plane and thus to improve the wafer planarity by introducing an impurity into the single crystal semiconductor more uniformly during the pulling of the single crystal semiconductor from a melt. In the course of pulling the single crystal semiconductor (6), the rotating velocity (?2) of the single crystal semiconductor (6) being pulled is adjusted to a predetermined value or higher, and a magnetic field having a strength in a predetermined range is applied to the melt (5). Particularly, the crystal peripheral velocity is adjusted to 0.126 m/sec or higher, and M/V1/3 is adjusted to 35.5?M/V1/3?61.3. More desirably, the crystal peripheral velocity is adjusted to 0.141 m/sec or higher, and M/V1/3 is adjusted to 40.3?M/V1/3?56.4.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: May 20, 2008
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Masafumi Ura, Hidetoshi Kurogi, Toshiharu Yubitani, Noboru Furuichi
  • Publication number: 20070131158
    Abstract: The method for manufacturing a single crystal semiconductor achieves an object to reduce the impurity concentration nonuniformity within a semiconductor wafer plane and thus to improve the wafer planarity by introducing an impurity into the single crystal semiconductor more uniformly during the pulling of the single crystal semiconductor from a melt. In the course of pulling the single crystal semiconductor (6), the rotating velocity (?2) of the single crystal semiconductor (6) being pulled is adjusted to a predetermined value or higher, and a magnetic field having a strength in a predetermined range is applied to the melt (5). Particularly, the crystal peripheral velocity is adjusted to 0.126 m/sec or higher, and M/V1/3 is adjusted to 35.5?M/V1/3?61.3. More desirably, the crystal peripheral velocity is adjusted to 0.141 m/sec or higher, and M/V1/3 is adjusted to 40.3?M/V1/3?56.4.
    Type: Application
    Filed: February 18, 2005
    Publication date: June 14, 2007
    Applicant: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
    Inventors: Masafumi Ura, Hidetoshi Kurogi, Toshiharu Yubitani, Noboru Furuichi
  • Patent number: 6162730
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping or grinding step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: December 19, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 5899743
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: May 4, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 5880027
    Abstract: The present invention provides a process for fabricating a semiconductor wafer, including surface-grinding both sides of the sliced wafer, and cleaning the surface-ground wafer with an alkaline solution to remove the sharp protruded part. The frictional resistance between the surface-ground wafer and a polishing cloth can be reduced, thus extending a life of a template and the polishing cloth.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: March 9, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirofumi Hajime, Toshiharu Yubitani
  • Patent number: 5873772
    Abstract: A method for polishing a semiconductor wafer is provided. A semiconductor wafer is detached from a polishing pad on a side of an upper polishing plate and is kept to be supported by a lower polishing plate. A contact area between the a wafer and the upper polishing plate is set to be less than a contact area between the wafer and the lower polishing plate. As a result, the wafer is definitely detached from the polishing pad on the side of the upper polishing plate and is to be kept supported by the lower polishing plate when the upper polishing plate is lifted.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: February 23, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirofumi Hajime, Toshiharu Yubitani
  • Patent number: 5821166
    Abstract: method of manufacturing semiconductor wafers, which can prevent the pendent surface phenomenon during the mirror polishing of the wafers and can enhance the flatness of the mirror polished surfaces. The method of manufacturing semiconductor wafers according to this invention includes slicing ingots into wafers, chamfering the peripheral edge portions of the wafers, lapping the sliced surfaces of the wafers, grinding the lapped surfaces of the wafers to form a gradual concave shape, mirror polishing the ground surfaces of the wafers, and finally cleaning the mirror polished wafers.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: October 13, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirofumi Hajime, Toshiharu Yubitani
  • Patent number: 5756399
    Abstract: The present invention provides a process for making a semiconductor wafer, including slicing an ingot to obtain wafers; surface-grinding both sides of each of the wafers; etching the wafers with an alkaline solution; chamfering the peripheral portion of each of the wafers; both-side polishing the wafers for mirror processing ; cleaning both sides of each of the wafers to remove the particles attached to the sides; and drying and cleaning the wafers. By employing the present process, the time for polishing the wafer can be shortened, and the semiconductor wafer can be made effectively.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: May 26, 1998
    Assignee: Komatsu Electronic Metals Co. Ltd.
    Inventors: Hirofumi Hajime, Toshiharu Yubitani