Patents by Inventor Toshihide Jinnai

Toshihide Jinnai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220278137
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Inventors: Hajime WATAKABE, Toshihide JINNAI, Ryo ONODERA, Akihiro HANADA
  • Patent number: 11362113
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 14, 2022
    Assignee: Japan Display Inc.
    Inventors: Hajime Watakabe, Toshihide Jinnai, Ryo Onodera, Akihiro Hanada
  • Publication number: 20220043316
    Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.
    Type: Application
    Filed: October 21, 2021
    Publication date: February 10, 2022
    Applicant: Japan Display Inc.
    Inventors: Toshihide JINNAI, Hajime WATAKABE, Akihiro HANADA, Ryo ONODERA, lsao SUZUMURA
  • Publication number: 20220029026
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Application
    Filed: October 13, 2021
    Publication date: January 27, 2022
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Tomoyuki ITO, Toshihide JINNAI, lsao SUZUMURA, Akihiro HANADA, Ryo ONODERA
  • Publication number: 20210405411
    Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI, Isao SUZUMURA, Hajime WATAKABE, Ryo ONODERA
  • Patent number: 11181792
    Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 23, 2021
    Assignee: JAPAN DISPLAY INC.
    Inventors: Toshihide Jinnai, Hajime Watakabe, Akihiro Hanada, Ryo Onodera, Isao Suzumura
  • Patent number: 11177388
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 16, 2021
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Tomoyuki Ito, Toshihide Jinnai, Isao Suzumura, Akihiro Hanada, Ryo Onodera
  • Publication number: 20210320158
    Abstract: The purpose of the present invention is to increase ON current of the oxide semiconductor thin film transistor. An example of the structure that attains the purpose is: a display device having a substrate and a thin film transistor of an oxide semiconductor formed on the substrate including: a thickness of a source region and a drain region is thicker than a thickness of a channel region of the oxide semiconductor, the channel region has projections at portions contacting the source region and the drain region, a thickness of the projection is thicker than a thickness of the center of the channel region, and a thickness of the projection is thicker than a thickness of the source region and the drain region.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI, Isao SUZUMURA, Hajime WATAKABE, Ryo ONODERA
  • Publication number: 20210134848
    Abstract: An object of the present invention is to provide a technology using which, in a thin film transistor using oxide semiconductor, the resistance of a channel region of the oxide semiconductor is made high, and at the same time the resistances of a source region and a drain region of the oxide semiconductor are made low. There is provided a semiconductor device including: a thin film transistor including oxide semiconductor, the oxide semiconductor including a channel region, a drain region, and a source region; a gate insulating film formed on the channel region; an aluminum oxide film formed on the gate insulating film; and a gate electrode formed on the aluminum oxide film, wherein the aluminum oxide film has a region that covers neither the drain region nor the source region in a plane view.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI
  • Publication number: 20210074736
    Abstract: The purpose of the present invention is to prevent the TFT in the semiconductor device is shorted by existence of a foreign substance. An example of the structure to solve the problem is: A semiconductor device comprising: a scan line extends in a first direction, a first signal line extends in a second direction, which crosses the first direction, a second signal line extends parallel to the first signal line, an electrode is disposed between the first signal line and the second signal line, wherein a first TFT connects with the second signal line in a vicinity of the second signal line, a second TFT connects with the electrode in a vicinity of the first signal line, the first TFT and the second TFT are formed from oxide semiconductors, the first TFT and the second TFT are connected in series.
    Type: Application
    Filed: August 19, 2020
    Publication date: March 11, 2021
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Toshihide JINNAI, Hajime WATAKABE, Ryo ONODERA
  • Publication number: 20210066351
    Abstract: There is provided a technique that enables a reduction in the display failure of a display device and the improvement of the yields of the display device in a display device that adopts a semiconductor device including a thin film transistor using an oxide semiconductor. A semiconductor device according to an embodiment includes a thin film transistor having an oxide semiconductor. The oxide semiconductor has a drain region, a source region, and a channel region provided between the drain region and the source region. The thin film transistor includes a gate insulating film provided on the channel region, an aluminum oxide film provided on the gate insulating film, an insulating film provided on the aluminum oxide film, and a gate electrode provided on the insulating film.
    Type: Application
    Filed: August 6, 2020
    Publication date: March 4, 2021
    Inventors: Hajime WATAKABE, Toshihide JINNAI, Ryo ONODERA, Akihiro HANADA
  • Publication number: 20200264484
    Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 20, 2020
    Applicant: Japan Display Inc.
    Inventors: Toshihide JINNAI, Hajime WATAKABE, Akihiro HANADA, Ryo ONODERA, lsao SUZUMURA
  • Publication number: 20200259020
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Tomoyuki ITO, Toshihide JINNAI, lsao SUZUMURA, Akihiro HANADA, Ryo ONODERA
  • Patent number: 10007138
    Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating film covering the semiconductor layer, a gate line extended in a first direction on the first insulating film to intersect the semiconductor layer, a second insulating film covering the gate line, a first common electrode formed on the second insulating film, a third insulating film covering the first common electrode, a source line which is extended in a second direction on the third insulating film and which is in contact with the semiconductor layer, and a fourth insulating film which covers the source line and which has a thickness greater than a thickness of the third insulating film.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: June 26, 2018
    Assignee: Japan Display Inc.
    Inventors: Toshihide Jinnai, Hirofumi Mizukoshi
  • Patent number: 9384965
    Abstract: According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface. The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: July 5, 2016
    Assignee: Japan Display Inc.
    Inventors: Naoya Ito, Toshihide Jinnai, Hirofumi Mizukoshi
  • Publication number: 20160116791
    Abstract: According to one embodiment, a display device includes a semiconductor layer, a first insulating film covering the semiconductor layer, a gate line extended in a first direction on the first insulating film to intersect the semiconductor layer, a second insulating film covering the gate line, a first common electrode formed on the second insulating film, a third insulating film covering the first common electrode, a source line which is extended in a second direction on the third insulating film and which is in contact with the semiconductor layer, and a fourth insulating film which covers the source line and which has a thickness greater than a thickness of the third insulating film.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 28, 2016
    Applicant: Japan Display Inc.
    Inventors: Toshihide JINNAI, Hirofumi MIZUKOSHI
  • Patent number: 9245910
    Abstract: According to one embodiment, provided is an array substrate that can effectively prevent an oxide conductive film and a silicon nitride film on the oxide conductive film from peeling without deteriorating reliability. A method for manufacturing the array substrate includes a surface treatment step and a nitride film forming step. In the surface treatment step, by plasma discharge, the oxide conductive film is cleaned without being reduced, and surface layers of the insulating film layer not covered by the oxide conductive film and portions of the insulating film layer in the regions covered by the oxide conductive film are etched to form recesses leading to portions under the oxide conductive film. In the nitride film forming step, successively from the surface treatment step, the silicon nitride film is formed by plasma CVD so as to cover the recesses and the oxide conductive film.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: January 26, 2016
    Assignee: Japan Display Inc.
    Inventors: Yasunori Fukumoto, Toshihide Jinnai, Koji Sato
  • Publication number: 20150177556
    Abstract: According to one embodiment, provided is an array substrate that can effectively prevent an oxide conductive film and a silicon nitride film on the oxide conductive film from peeling without deteriorating reliability. A method for manufacturing the array substrate includes a surface treatment step and a nitride film forming step. In the surface treatment step, by plasma discharge, the oxide conductive film is cleaned without being reduced, and surface layers of the insulating film layer not covered by the oxide conductive film and portions of the insulating film layer in the regions covered by the oxide conductive film are etched to form recesses leading to portions under the oxide conductive film. In the nitride film forming step, successively from the surface treatment step, the silicon nitride film is formed by plasma CVD so as to cover the recesses and the oxide conductive film.
    Type: Application
    Filed: November 19, 2014
    Publication date: June 25, 2015
    Applicant: Japan Display Inc.
    Inventors: Yasunori FUKUMOTO, Toshihide JINNAI, Koji SATO
  • Publication number: 20150140794
    Abstract: According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface . The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 21, 2015
    Applicant: Japan Display Inc.
    Inventors: Naoya ITO, Toshihide Jinnai, Hirofumi Mizukoshi
  • Patent number: 6130119
    Abstract: A method of manufacturing a conductive film-attached substrate wherein a nitride film is formed on an insulating substrate and on at least part of an oxide conductive film formed on the substrate, which is characterized in that after a first silicon nitride film is formed in an atmosphere which is incapable of inducing a reductive effect on the oxide conductive film, a second silicon nitride film is superimposed on the first silicon nitride film under a condition which enables to achieve a faster film-forming rate than that of the first silicon nitride film.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: October 10, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshihide Jinnai