Abstract: Upon receiving an interrupt request via any one from among multiple first interrupt signal lines, a serializer identifies an error device which is one device from among the multiple devices that has transmitted the interrupt request and transmits the identification number of the error device to a deserializer. Furthermore, the serializer reads status information from the error device via a first interface and transmits the status information of the error device to the deserializer. The deserializer is structured to store the identification number of the error device and the status information in its internal register, and of transmitting an interrupt request to a controller via a second interrupt signal line. The deserializer transmits the identification number of the error device and the status information to the controller in response to a read command received from the controller.

Abstract: Differential input pins are coupled to a differential transmission path. A receiver circuit receives a differential input signal input via the differential input pins. A latch circuit latches an internal differential signal output from the receiver circuit. An evaluation circuit samples the internal differential signal, and generates evaluation data with respect to the waveform of the internal differential signal. A reception device is configured to be capable of providing evaluation data DEVAL to an external circuit.

Abstract: Differential input pins are coupled to a differential transmission path. A receiver circuit receives a differential input signal input via the differential input pins. A latch circuit latches an internal differential signal output from the receiver circuit. An evaluation circuit samples the internal differential signal, and generates evaluation data with respect to the waveform of the internal differential signal. A reception device is configured to be capable of providing evaluation data DEVAL to an external circuit.

Abstract: A first receiver receives second serial data transmitted from a second circuit. A second receiver receives first serial data transmitted from a first circuit. An automatic adjustment circuit generates a control signal so as to reduce an error rate of the first serial data received by the second receiver. A second driver drives a differential transmission path according to the second serial data including the control signal. An operation parameter of a first driver is set based on the control signal included in the second serial data.

Abstract: A first receiver receives second serial data transmitted from a second circuit. A second receiver receives first serial data transmitted from a first circuit. An automatic adjustment circuit generates a control signal so as to reduce an error rate of the first serial data received by the second receiver. A second driver drives a differential transmission path according to the second serial data including the control signal. An operation parameter of a first driver is set based on the control signal included in the second serial data.

Abstract: A timing controller is connected via a common bus to multiple data drivers which drive a display panel. A reception interface circuit receives image data including each color (R, G, and B). A timing control unit controls the timing of the luminance data for each color, i.e., R, G, and B, such that it conforms to the multiple data drivers provided as the transmission destinations. A transmission interface circuit transmits the luminance data for each color, the timing of which is controlled by the timing control unit, and a synchronization clock, to the multiple data drivers via the common bus. The transmission interface circuit is configured so as to independently adjust the respective phases of the synchronization clock and the luminance data for each color to be output to the bus.