Abstract: A wiring substrate includes a core layer, first conductor layers including a first inner conductor layer, a first outer conductor layer and a first intermediate conductor layer, second conductor layers including a second inner conductor layer, a second outer conductor layer and a second intermediate conductor layer, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, and the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer and includes a conductor pattern formed such that an upper surface of the conductor pattern has an edge portion forming an inclined portion inclined toward the core layer.

Abstract: A wiring board includes core substrate, a first build-up layer on first surface of the substrate and including conductive and insulating resin layers, and a second build-up layer on second surface of the substrate and including conductive and insulating resin layers. The first build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer, and the second build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, interlayer insulating layers interposed between the first conductor layers and between the second conductor layers, and via conductors formed in the core layer such that each via conductor decreases in diameter from one of the inner conductor layers toward the other one of the inner conductor layers and that the other one of the inner conductor layers has thickness greater than thickness of the one of the inner conductor layers. The first and/or second inner conductor layers includes a first laminated structure including metal foil and plating film layers, the first and/or second outer conductor layers includes the first laminated structure, and the first and/or second intermediate conductor layers includes a second laminated structure including metal foil and plating film layers.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate layers, second conductor layers including second inner, outer and intermediate layers, interlayer insulating layers interposed between the first conductor layers and between the second conductor layers, and via conductors formed in the insulating layers such that each via conductor connects two conductor layers and is integrally formed with one of the conductor layers on side away from the core layer. The first and/or second inner conductor layers has a first conductor layer structure including metal foil and plating film layers, the first and/or second outer conductor layers has the first structure, the first and/or second intermediate conductor layers has a second conductor layer structure including metal foil and plating film layers, and the via conductors include a group integrally formed with the first structure and including constricted via conductors each having a constricted portion.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including metal foil and plating film layers and includes first conductor pattern having a side surface curved toward inner side of the first pattern, the first and/or second outer conductor layers has the first laminated structure and includes the first conductor pattern having the side surface curved toward the inner side of the first pattern, and the first and/or second intermediate conductor layers has a second laminated structure including metal foil and plating film layers and includes second conductor pattern having a side surface curved toward outer side of the second pattern.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer, and the first and second laminated structures are formed such that a surface of the second laminated structure on a side away from the core layer has unevenness smaller than unevenness of a surface of the first laminated structure on a side away from the core layer.

Abstract: A wiring board includes core substrate, a first build-up layer on first surface of the substrate and including conductive and insulating resin layers, and a second build-up layer on second surface of the substrate and including conductive and insulating resin layers. The first build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of each conductive layer on a non-outermost resin layer, and the second build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of each conductive layer on a non-outermost resin layer.

Abstract: A wiring substrate includes a core layer, first conductor layers including a first inner conductor layer, a first outer conductor layer and a first intermediate conductor layer, second conductor layers including a second inner conductor layer, a second outer conductor layer and a second intermediate conductor layer, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, and the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer and includes a conductor pattern formed such that an upper surface of the conductor pattern has an edge portion forming an inclined portion inclined toward the core layer.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate layers, second conductor layers including second inner, outer and intermediate layers, interlayer insulating layers interposed between the first conductor layers and between the second conductor layers, and via conductors formed in the insulating layers such that each via conductor connects two conductor layers and is integrally formed with one of the conductor layers on side away from the core layer. The first and/or second inner conductor layers has a first conductor layer structure including metal foil and plating film layers, the first and/or second outer conductor layers has the first structure, the first and/or second intermediate conductor layers has a second conductor layer structure including metal foil and plating film layers, and the via conductors include a group integrally formed with the first structure and including constricted via conductors each having a constricted portion.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including metal foil and plating film layers and includes first conductor pattern having a side surface curved toward inner side of the first pattern, the first and/or second outer conductor layers has the first laminated structure and includes the first conductor pattern having the side surface curved toward the inner side of the first pattern, and the first and/or second intermediate conductor layers has a second laminated structure including metal foil and plating film layers and includes second conductor pattern having a side surface curved toward outer side of the second pattern.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, interlayer insulating layers interposed between the first conductor layers and between the second conductor layers, and via conductors formed in the core layer such that each via conductor decreases in diameter from one of the inner conductor layers toward the other one of the inner conductor layers and that the other one of the inner conductor layers has thickness greater than thickness of the one of the inner conductor layers. The first and/or second inner conductor layers includes a first laminated structure including metal foil and plating film layers, the first and/or second outer conductor layers includes the first laminated structure, and the first and/or second intermediate conductor layers includes a second laminated structure including metal foil and plating film layers.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer, and the first and second laminated structures are formed such that a surface of the second laminated structure on a side away from the core layer has unevenness smaller than unevenness of a surface of the first laminated structure on a side away from the core layer.

Abstract: A wiring board includes core substrate, a first build-up layer on first surface of the substrate and including conductive and insulating resin layers, and a second build-up layer on second surface of the substrate and including conductive and insulating resin layers. The first build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer, and the second build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer.

Abstract: A printed wiring board includes a core substrate having cavity to accommodate an electronic component and including a front conductor layer formed on front side of the core substrate, and a back conductor layer formed on back side of the core substrate, through-hole conductors formed through the core substrate such that the through-hole conductors connect the front and back conductor layers of the core substrate, a front build-up layer formed on front surface of the core substrate and including interlayer insulating layers and conductor layers, and a back build-up layer formed on back surface of the core substrate and including interlayer insulating layers and conductor layers. The conductor layers in the front build-up layer include a conductor layer sandwiching one of the interlayer insulating layers with the front conductor layer such that the conductor layer and the front conductor layer have the same electric potential in region surrounding the cavity.

Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. The core substrate includes a core layer, through-hole conductors and through-hole lands. Metal foils of the through-hole lands in the core substrate have mat surfaces at interfaces of the core layer in the core substrate, metal foils of via lands in the build-up layers have inner mat surfaces at interfaces of insulating layers, and metal foils of outermost conductor layers in the build-up layers have outermost mat surfaces at interfaces of outermost insulating layers. Ten-point average roughness (RzI1) of the inner first mat surface is smaller than each often-point average roughness (Rz1, Rz2) of the mat surfaces and ten-point average roughness (RzO1, RzO2) of the outermost mat surfaces. Ten-point average roughness (RzI2) of the inner second mat surface is smaller than each of the ten-point average roughness (Rz1, Rz2, RzO1, RzO2).

Abstract: A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.

Abstract: A printed wiring board includes: a core substrate having a core layer and first and second conductor layers; a first build-up layer including a first insulating layer, an inner first conductor layer, an outermost first insulating layer, and an outermost first conductor layer; and a second build-up layer including a second insulating layer, an inner second conductor layer, an outermost second insulating layer, and an outermost second conductor layer. Each conductor layer includes metal foil, seed layer, and electrolytic plating film, t1/T1, t2/T2, u1/U1 and u2/U2 are smaller than 1, and s1/S1 and s2/S2 are larger than 1, where t1, t2, u1, u2, s1 and s2 are electrolytic plating film thicknesses of the first and second and outermost and inner first and second conductor layers, T1, T2, U1, U2, S1 and S2 are metal foil thicknesses of the first and second and outermost and inner first and second conductor layers.

Abstract: A printed wiring board includes: a core substrate having a core layer, conductor layers on the core layer, and through-hole conductors; a first build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer; and a second build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer. Each of the conductor layers, inner side conductor layers, and outermost conductor layers has a metal foil, a seed layer and an electrolytic plating film, and that each inner side conductor layer has the smallest thickness among the conductor layers, inner side conductor layers and outermost conductor layers.

Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. The core substrate includes a core layer, through-hole conductors and through-hole lands. Metal foils of the through-hole lands in the core substrate have mat surfaces at interfaces of the core layer in the core substrate, metal foils of via lands in the build-up layers have inner mat surfaces at interfaces of insulating layers, and metal foils of outermost conductor layers in the build-up layers have outermost mat surfaces at interfaces of outermost insulating layers. Ten-point average roughness (RzI1) of the inner first mat surface is smaller than each of ten-point average roughness (Rz1, Rz2) of the mat surfaces and ten-point average roughness (RzO1, RzO2) of the outermost mat surfaces. Ten-point average roughness (RzI2) of the inner second mat surface is smaller than each of the ten-point average roughness (Rz1, Rz2, RzO1, RzO2).

Abstract: A multilayer wiring board includes a base substrate including conductor layers and insulating layers formed such that the conductor layers and the insulating layers are laminated alternately and that the conductor layers include a first conductor pattern, an inter-pattern insulating resin layer formed on a surface of the base substrate and including an insulating resin layer and an insulating base material laminated on the insulating resin layer such that resin forming the insulating resin layer is filling gaps formed between portions of the first conductor pattern, and a second conductor pattern formed on an outer layer side of the first conductor pattern such that the inter-pattern insulating resin layer is formed between the first conductor pattern and the second conductor pattern. The base substrate, the inter-pattern insulating resin layer and the second conductor pattern form an antenna portion.