Abstract: An inspection jig is used for inspection for an inspection target device including a flexible substrate having a flexible base material with external connection terminals formed thereon. The inspection jig is composed of an inspection device and an attraction part. The inspection device has inspection terminals, and the inspection terminals have vacuum attraction holes. The attraction part has an attraction surface. The external connection terminals have first through holes. In inspection, the attraction part is placed on the front surface of the flexible base material so that the first through holes and the vacuum attraction holes overlap each other and the attraction surface covers the first through holes, and the insides of the first through holes and the vacuum attraction holes are made into vacuum, whereby the attraction surface is attracted to the flexible base material and the external connection terminals are attracted to the inspection terminals.

Abstract: An inspection jig is used for inspection for an inspection target device including a flexible substrate having a flexible base material with external connection terminals formed thereon. The inspection jig is composed of an inspection device and an attraction part. The inspection device has inspection terminals, and the inspection terminals have vacuum attraction holes. The attraction part has an attraction surface. The external connection terminals have first through holes. In inspection, the attraction part is placed on the front surface of the flexible base material so that the first through holes and the vacuum attraction holes overlap each other and the attraction surface covers the first through holes, and the insides of the first through holes and the vacuum attraction holes are made into vacuum, whereby the attraction surface is attracted to the flexible base material and the external connection terminals are attracted to the inspection terminals.

Abstract: An integrated circuit includes an amplifier for amplifying an electric current signal from an external light receiving element, and a low-pass filter. The low-pass filter has a resistor and a capacitor serial-connection in which multiple capacitive elements are serially connected. With respect to the resistor in the low-pass filter, one end thereof is connected to a power terminal to which the bias voltage is inputted, and the other end thereof is connected to an input terminal of the capacitor serial-connection and to a bias application electrode of the light receiving element through which the bias voltage is applied. With respect to the capacitor serial-connection in the low-pass filter, each connection terminal between two of the serially connected capacitive elements and an output terminal of the capacitor serial-connection, are connected to their respective capacitance terminals to which a ground potential as a reference for the bias voltage is connected selectively.

Abstract: An integrated circuit includes an amplifier for amplifying an electric current signal from an external light receiving element, and a low-pass filter. The low-pass filter has a resistor and a capacitor serial-connection in which multiple capacitive elements are serially connected. With respect to the resistor in the low-pass filter, one end thereof is connected to a power terminal to which the bias voltage is inputted, and the other end thereof is connected to an input terminal of the capacitor serial-connection and to a bias application electrode of the light receiving element through which the bias voltage is applied. With respect to the capacitor serial-connection in the low-pass filter, each connection terminal between two of the serially connected capacitive elements and an output terminal of the capacitor serial-connection, are connected to their respective capacitance terminals to which a ground potential as a reference for the bias voltage is connected selectively.

Abstract: A plurality of source-grounded transistors (3) are connected in parallel with each other, and a plurality of gate-grounded transistors (4) are connected in parallel with each other. Sources (4s) of the plurality of gate-grounded transistors (4) are connected to drains (3d) of the plurality of source-grounded transistors (3) respectively. Ground pads (5) are connected to sources (3s) of the plurality of source-grounded transistors (3). A plurality of grounding capacitances (6) are connected between gates (4g) of the plurality of gate-grounded transistors (4) and the ground pads (5). The plurality of source-grounded transistors (3) and the plurality of grounding capacitances (6) are alternately arranged between the ground pads (5) and the plurality of gate-grounded transistors (4).

Abstract: A differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals. The second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting drain current of the first transistor in response to an externally applied current or voltage.

Abstract: A differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals. The second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting drain current of the first transistor in response to an externally applied current or voltage.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P?pocket regions 17 and N?pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P?pocket regions 17 and the N?pocket regions 27.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P? pocket regions 17 and N? pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P? pocket regions 17 and the N? pocket regions 27.

Abstract: A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal, a binary comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal, a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value, and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P? pocket regions 17 and N? pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P? pocket regions 17 and the N? pocket regions 27.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P31 pocket regions 17 and N31 pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P31 pocket regions 17 and the N31 pocket regions 27.

Abstract: A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.

Abstract: A semiconductor device includes a semiconductor substrate, an insulated gate type transistor formed in the semiconductor substrate, and an insulated gate type capacitor formed in the semiconductor substrate. The insulated gate type transistor includes a gate insulating film of the transistor selectively formed on the semiconductor substrate, a gate electrode of the transistor formed on the gate insulating film of the transistor, and source-drain regions formed to interpose a body region of the transistor provided under the gate electrode of the transistor in a surface of the semiconductor substrate. The insulated gate type capacitor includes a gate insulating film of the capacitor selectively formed on the semiconductor substrate, a gate electrode of the capacitor formed on the gate insulating film of the capacitor, and extraction electrode regions formed to interpose a body region of the capacitor provided under the gate electrode of the capacitor in the surface of the semiconductor substrate.

Abstract: A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal, a binary comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal, a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value, and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P? pocket regions 17 and N? pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P? pocket regions 17 and the N? pocket regions 27.

Abstract: A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.

Abstract: A phase comparator includes a phase comparison unit performing a phase comparison. The phase comparison unit carries out a switching operation according to the exclusive OR between two signals to be compared and passes or receives a current to or from an output node according to a resultant phase difference. The exclusive OR is associated with the switching operation of two transistors. Namely, when one of the two transistors is turned on, the result of the exclusive OR is L level. Accordingly, the charging/discharging time for an output signal of a logic circuit is shortened and a stable phase comparison can be performed.

Abstract: A phase comparator includes a phase comparison unit performing a phase comparison. The phase comparison unit carries out a switching operation according to the exclusive OR between two signals to be compared and passes or receives a current to or from an output node according to a resultant phase difference. The exclusive OR is associated with the switching operation of two transistors. Namely, when one of the two transistors is turned on, the result of the exclusive OR is L level. Accordingly, the charging/discharging time for an output signal of a logic circuit is shortened and a stable phase comparison can be performed.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.