Abstract: An apparatus includes a first port coupled to a first apparatus through a ring line, a second port coupled to a second apparatus through a second line, the second apparatus disposed external to the ring line, the second line configured redundantly with a first line between the first apparatus and the second apparatus, a third port coupled to the first apparatus through a control line for a control signal concerning the first line, and circuitry that detects a fault in the control line, wherein the circuitry detects a fault in the second line, switches the second line from an active line to a standby line in accordance with the detection of the fault in the second line, and while the fault in the control line is detected, shuts down the first port in accordance with the detection of the fault in the second line.

Abstract: An apparatus includes a first port coupled to a first apparatus through a ring line, a second port coupled to a second apparatus through a second line, the second apparatus disposed external to the ring line, the second line configured redundantly with a first line between the first apparatus and the second apparatus, a third port coupled to the first apparatus through a control line for a control signal concerning the first line, and circuitry that detects a fault in the control line, wherein the circuitry detects a fault in the second line, switches the second line from an active line to a standby line in accordance with the detection of the fault in the second line, and while the fault in the control line is detected, shuts down the first port in accordance with the detection of the fault in the second line.

Abstract: A circuit device has a first output buffer including a first adjustment circuit for adjusting a level of the first output signal, a first input buffer connected to the first output buffer, an adjustment controller for outputting a test signal to the first output buffer, outputting a control signal to the first adjustment circuit so that the level of the first output signal is adjusted on the basis of the control signal, monitoring an output of the first input buffer, and adjusting the control signal on the basis of the monitoring the output of the first input buffer, a second output buffer connected to the adjustment controller and operable to assume either an active or a non-active state, for outputting a second output signal when controlled to assume an active state, including a second adjustment circuit, and a second input buffer.

Abstract: A circuit device has a first output buffer including a first adjustment circuit for adjusting a level of the first output signal, a first input buffer connected to the first output buffer, an adjustment controller for outputting a test signal to the first output buffer, outputting a control signal to the first adjustment circuit so that the level of the first output signal is adjusted on the basis of the control signal, monitoring an output of the first input buffer, and adjusting the control signal on the basis of the monitoring the output of the first input buffer, a second output buffer connected to the adjustment controller and operable to assume either an active or a non-active state, for outputting a second output signal when controlled to assume an active state, including a second adjustment circuit, and a second input buffer.

Abstract: A construction is adopted in which an annular spacer 27 is held between first and second inner races 2a, 2b. An internal clearance in a double-row bearing unit is measured in a middle step of assembling work of a wheel supporting bearing assembly, and in the event that a resultant measured value does not become a proper value, an axial dimension of the spacer 27 is adjusted, so that the internal clearance becomes the proper value. Thereafter, the assembling work is made to continue until the assembling work is completed. A problem which is to be solved by the invention is solved in the way described above.

Abstract: A data width conversion apparatus has a buffer for storing output-incomplete partial data of input data received in the past and a block shifter for combining the output-incomplete partial data stored in said buffer with new input data. In the combined data by the block shifter, a portion of a fixed data width is outputted in form of an output data, and data less than the fixed data width or data exceeding the fixed data width is stored in the buffer so as to be combined with the successive input data.

Abstract: A multiprocessor system having the capability of increasing the speed of a bus clock while retaining high reliability and fault tolerant performance as well as utilizing the current operating system resources. The multiprocessor system is made up of a plurality of processor modules connected together through a duplicated system bus. The duplicated system bus is divided into a plurality of segments, and these segments are coupled together by at least one bus extender mechanism. The multiprocessor system is also provided with first notification means which is provided between bus control mechanisms for controlling the states of physical buses and the bus extender mechanism, and the bus control mechanisms and the bus extender mechanism are mutually notified of the state of each mechanism through the first notification means.