Abstract: To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR1), a second transistor region (TR2) arranged between the first side and TR1, and a dummy region on the first direction side of TR1. TR1 has a first channel forming region facing the first side. TR2 has a second channel forming region facing the first side. The first channel forming region has a non-facing region that is not facing the second channel forming region. The dummy region faces the non-facing region in the second direction.

Abstract: To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR1), a second transistor region (TR2) arranged between the first side and TR1, and a dummy region on the first direction side of TR1. TR1 has a first channel forming region facing the first side. TR2 has a second channel forming region facing the first side. The first channel forming region has a non-facing region that is not facing the second channel forming region. The dummy region faces the non-facing region in the second direction.

Abstract: A lever member of a lever assisted insertion device engages with a front frame of a shelf before a fully inserted position of a substrate unit to form a leverage fulcrum on the front frame. A force that an operator applies to the lever member is transmitted to the substrate unit via a point of application with respect to the fulcrum, thereby inserting the substrate unit up to the fully inserted position. A buffering device abuts against the front frame of the shelf within a depth range of a front panel of the substrate unit before an operation start position at which the lever member engages with the front frame of the shelf, to absorb impact of the substrate unit at the time of insertion.

Abstract: A semiconductor device includes an electrode (electrode pad), an insulation film (for example, protective resin film) formed over the electrode and having an opening for exposing the electrode. The semiconductor device further includes an under bump metal (UBM layer) formed over the insulation film and connected by way of the opening 5a to the electrode, and a solder ball formed over the under bump metal. In the under bump metal, a thickness A for the first portion situated in the opening above the electrode and the thickness B for the second portion situated in the under bump metal at the periphery of the opening over the insulation film are in a condition: A/B?1.5, and the opening and the solder ball are in one to one correspondence.

Abstract: A semiconductor device according to this embodiment has an electrode (electrode pad) and an insulative film (protective resin film) formed on the electrode and having an opening for exposing the electrode. The semiconductor device further has an under bump metal (UBM layer) formed over the insulative film and connected with the electrode through the opening, and a solder ball formed over the under bump metal, and the contour line at the lower end of the solder ball is situated inside the contour line of the under bump metal, whereby generation of fracture in the insulative film caused by the stress upon mounting the semiconductor device is suppressed even when the solder ball is formed of a lead-free solder.

Abstract: The delay time variation of transistors caused by the manufacturing variation is desired to be adjusted. A relation table storing a relation between sizes and voltage values (supply voltages and bias voltages) is provided. Macros each of which includes a transistor and a setting voltage generation circuit for applying a setting voltage to the transistor are formed on a chip. A process data indicating a size of the transistor is generated. The voltage value corresponding to the size of the transistor indicated by the process data in the relation table is selected as an optimum voltage value (supply voltage Vdd, bias voltage Bias) for each of the macros. The setting voltage of each of the macros is set to the optimum voltage value. The delay time can be adjusted without requiring a detection circuit for detecting the delay time.

Abstract: A lever member of a lever assisted insertion device engages with a front frame of a shelf before a fully inserted position of a substrate unit to form a leverage fulcrum on the front frame. A force that an operator applies to the lever member is transmitted to the substrate unit via a point of application with respect to the fulcrum, thereby inserting the substrate unit up to the fully inserted position. A buffering device abuts against the front frame of the shelf within a depth range of a front panel of the substrate unit before an operation start position at which the lever member engages with the front frame of the shelf, to absorb impact of the substrate unit at the time of insertion.

Abstract: To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR1), a second transistor region (TR2) arranged between the first side and TR1, and a dummy region on the first direction side of TR1. TR1 has a first channel forming region facing the first side. TR2 has a second channel forming region facing the first side. The first channel forming region has a non-facing region that is not facing the second channel forming region. The dummy region faces the non-facing region in the second direction.

Abstract: The delay time variation of transistors caused by the manufacturing variation is desired to be adjusted. A relation table storing a relation between sizes and voltage values (supply voltages and bias voltages) is provided. Macros each of which includes a transistor and a setting voltage generation circuit for applying a setting voltage to the transistor are formed on a chip. A process data indicating a size of the transistor is generated. The voltage value corresponding to the size of the transistor indicated by the process data in the relation table is selected as an optimum voltage value (supply voltage Vdd, bias voltage Bias) for each of the macros. The setting voltage of each of the macros is set to the optimum voltage value. The delay time can be adjusted without requiring a detection circuit for detecting the delay time.

Abstract: There has been a problem of damaging a diffusion layer 4 occasionally in etching of a nitride film 5 in a wide gate pitch P1 region. First, a plurality of diffusion layers 4, gates 2 and sidewalls 3 are formed on a silicon substrate 1, so as to be adjacent to each other. Next, a nitride film 5 is stacked on the diffusion layers 4, the gates 2 and the sidewalls 3, so that the surface of the film reaches a level higher than the top surface of the gates 2, and so as to fill up the entire portion of gaps in a narrow gate pitch P region. Next, the surface of the nitride film 5 is planarized, and further on the nitride film 6, an insulating oxide film 6 is stacked. Contact holes 7 are then formed, and a connection plug 8 is formed in each of the holes.

Abstract: A resin composition comprising (a) 100 parts by weight of a block copolymer composed of polyphenylene sulfide segments and polyphenylene sulfide sulfone segments and (b) 0.01 to 20 parts by weight of at least one compound selected from the group consisting of epoxy resins, maleimide compounds, N,N'-diarylcarbodiimide compounds and organosilane compounds and as required, (c) an organic filler.

Abstract: A polyarylene sulfide resin composition comprising (A) 100 parts by weight of a polyarylene sulfide resin, (B) 0.01 to 30 parts of a polymer containing a fluoro-aliphatic group and having affinity for the resin (A) and a graft or block copolymer having affinity for the resin (A) and hydrophilicity and (C) 0 to 600 parts by weight of a filler. The composition is suitable for use as an encapsulation on material for electronic component parts and a coating agent.

Abstract: A polyphenylene sulfide resin composition comprising (1) a polyphenylene sulfide resin having a melt flow value of at least 1,000 g/min., (2) silicic acid and/or a silicate, and (3) a silane compound composed of a vinylsilane and an aminosilane and/or an epoxysilane.