Abstract: The data transfer has room for improvement of reduction in the operating electric current flowing on the signal bus and correct acquisition of the large amount of data. Each of data, a first clock signal and a second clock signal, a phase of which shifts by a predetermined amount from the first clock signal, has an amplitude that is smaller than an amplitude of a power supply voltage, and each of a semiconductor device and a memory device takes input of data in synchronization with rise edges of first and second clock signals.

Abstract: The data transfer has room for improvement of reduction in the operating electric current flowing on the signal bus and correct acquisition of the large amount of data. Each of data, a first clock signal and a second clock signal, a phase of which shifts by a predetermined amount from the first clock signal, has an amplitude that is smaller than an amplitude of a power supply voltage, and each of a semiconductor device and a memory device takes input of data in synchronization with rise edges of first and second clock signals.

Abstract: A stack memory includes a base chip, a memory chip stacked over the base chip, and a via 42 provided between the base chip and the memory chip. The base chip has an external interface circuit and a late write control circuit. The external interface circuit externally receives/transmits write data and read data. The late write control circuit has at least a register storing write data externally supplied through the external interface circuit. The memory chip has a memory cell array and a late write control circuit having at least a register storing write data supplied from the register through the via.

Abstract: A stack memory includes a base chip, a memory chip stacked over the base chip, and a via 42 provided between the base chip and the memory chip. The base chip has an external interface circuit and a late write control circuit. The external interface circuit externally receives/transmits write data and read data. The late write control circuit has at least a register storing write data externally supplied through the external interface circuit. The memory chip has a memory cell array and a late write control circuit having at least a register storing write data supplied from the register through the via.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Abstract: A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal.

Abstract: In writing N level of multilevel data to nonvolatile semiconductor memory by repeating a verification process, a verification result of a memory cell where the Nth threshold level which is the highest level is to be written as an expected level is invalidated until completion of writing to a memory cell where the (N?1)th and lower level is to be written. The verification result of the memory cell where the Nth level is to be written is validated after reaching the (N?1)th write level. A reference current supplied to a sense amplifier corresponding to the Nth level is set at at least a level allowing no indeterminate sensing of a sense amplifier. In verification of the Nth level data, a word line voltage supplied for verify-reading is raised from VW 1 to VW 2.

Abstract: In writing N level of multilevel data to nonvolatile semiconductor memory by repeating a verification process, a verification result of a memory cell where the Nth threshold level which is the highest level is to be written as an expected level is invalidated until completion of writing to a memory cell where the (N−1)th and lower level is to be written. The verification result of the memory cell where the Nth level is to be written is validated after reaching the (N−1)th write level. A reference current supplied to a sense amplifier corresponding to the Nth level is set at at least a level allowing no indeterminate sensing of a sense amplifier. In verification of the Nth level data, a word line voltage supplied for verify-reading is raised from VW 1 to VW 2.