Patents by Inventor Toshihiko Himeno
Toshihiko Himeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100318729Abstract: A NAND type flash memory having a program verifying function is provided, which can search for stored data at high speed. The flash memory reads search data that corresponds to stored data stored in a block in a front page of the block in a reverse-order search mode, compares the search data with the non-search data from a controller, and returns a block address and a page address of the search data that matches with the non-search data to the controller. At this time, the flash memory checks the match between the search data and the non-search data by comparing “0” data using the program verifying function provided in the flash memory itself.Type: ApplicationFiled: June 7, 2010Publication date: December 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Toshihiko HIMENO
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Patent number: 7826268Abstract: A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires.Type: GrantFiled: September 23, 2008Date of Patent: November 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Norihiro Fujita, Toshihiko Himeno, Hitoshi Shiga
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Patent number: 7685552Abstract: This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.Type: GrantFiled: March 26, 2007Date of Patent: March 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Fujio Ishihara, Ryubi Okuda, Toshihiko Himeno, Hiroshige Fujii
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Patent number: 7619921Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.Type: GrantFiled: September 11, 2006Date of Patent: November 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Toshihiko Himeno, Kenichi Imamiya, Hiroshi Nakamura
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Publication number: 20090126024Abstract: The management of software licenses becomes easy without incurring an increase in costs to effectively prevent software applications from unauthorized use. The software license managing method including: judging, when a software program installed in a computer is executed, whether or not a memory card having a predetermined ID is connected to said computer by an ID extracting and verifying program; permitting execution of said software program if the ID extracting and verifying program judges that said memory card is connected to said computer; inhibiting execution of said software program if the ID extracting and verifying program judges that said memory card is not connected to said computer.Type: ApplicationFiled: January 5, 2009Publication date: May 14, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Toshihiko HIMENO
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Publication number: 20090080261Abstract: A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires.Type: ApplicationFiled: September 23, 2008Publication date: March 26, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norihiro Fujita, Toshihiko Himeno, Hitoshi Shiga
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Patent number: 7421609Abstract: Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.Type: GrantFiled: July 14, 2005Date of Patent: September 2, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Toshihiko Himeno
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Patent number: 7313022Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.Type: GrantFiled: January 11, 2005Date of Patent: December 25, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Ken Takeuchi, Tamio Ikehashi, Toshihiko Himeno
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Publication number: 20070240087Abstract: This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.Type: ApplicationFiled: March 26, 2007Publication date: October 11, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fujio ISHIHARA, Ryubi Okuda, Toshihiko Himeno, Hiroshige Fujii
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Patent number: 7262636Abstract: Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same input capacitance and feedback current as the baseline drive circuit. The input of such a circuit may be coupled to three nodes, one of which is an inverter coupled to the logic to be driven, the second of which is dummy logic, and the third of which is an inverter the output of which is left floating.Type: GrantFiled: June 16, 2005Date of Patent: August 28, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Toshihiko Himeno, Stephen D. Weitzel
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Publication number: 20070016816Abstract: Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.Type: ApplicationFiled: July 14, 2005Publication date: January 18, 2007Inventor: Toshihiko Himeno
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Publication number: 20070016738Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.Type: ApplicationFiled: September 11, 2006Publication date: January 18, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koji Hosono, Toshihiko Himeno, Kenichi Imamiya, Hiroshi Nakamura
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Publication number: 20060284648Abstract: Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same input capacitance and feedback current as the baseline drive circuit. The input of such a circuit may be coupled to three nodes, one of which is an inverter coupled to the logic to be driven, the second of which is dummy logic, and the third of which is an inverter the output of which is left floating.Type: ApplicationFiled: June 16, 2005Publication date: December 21, 2006Inventors: Toshihiko Himeno, Stephen Weitzel
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Patent number: 7126851Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.Type: GrantFiled: November 17, 2004Date of Patent: October 24, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Toshihiko Himeno, Kenichi Imamiya, Hiroshi Nakamura
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Patent number: 6970388Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.Type: GrantFiled: November 3, 2003Date of Patent: November 29, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Ken Takeuchi, Tamio Ikehashi, Toshihiko Himeno
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Publication number: 20050125595Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.Type: ApplicationFiled: January 11, 2005Publication date: June 9, 2005Applicant: KABUSHHIKI KAISHA TOSHIBAInventors: Ken Takeuchi, Tamio Ikehashi, Toshihiko Himeno
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Publication number: 20050094478Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.Type: ApplicationFiled: November 17, 2004Publication date: May 5, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Toshihiko Himeno, Kenichi Imamiya, Hiroshi Nakamura
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Patent number: 6831859Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.Type: GrantFiled: November 10, 2003Date of Patent: December 14, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Toshihiko Himeno, Kenichi Imamiya, Hiroshi Nakamura
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Patent number: 6819596Abstract: In a method of testing a nonvolatile semiconductor memory integrated on a semiconductor chip comprising a memory cell array, a first register that stores an address of a defective region in the memory cell array, a plurality of internal voltage generator circuits, and a second register, the second register storing a trimming value for setting an internal voltage value generated by each of the internal voltage generator circuits, the testing method carries out resetting the address of the defective region stored in the first register and the trimming value stored in the second register, and setting the address of the defective region stored in the first register and the trimming value stored in the second register to a value according to a property of each of the semiconductor chips, wherein the testing is carried out without turning a power supply off after the power supply has been turned on.Type: GrantFiled: September 3, 2003Date of Patent: November 16, 2004Assignee: Kabushikia Kaisha ToshibaInventors: Tamio Ikehashi, Ken Takeuchi, Toshihiko Himeno
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Publication number: 20040090847Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.Type: ApplicationFiled: November 3, 2003Publication date: May 13, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ken Takeuchi, Tamio Ikehashi, Toshihiko Himeno