Patents by Inventor Toshihiko Iryu

Toshihiko Iryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5349219
    Abstract: A wafer-scale semiconductor integrated circuit device includes a wafer, a plurality of chips formed on the wafer, each of the chips having an internal logic circuit, interconnection lines mutually connecting the chips, and clamping circuits which are coupled to chips from among the chips which are located at a periphery of an arrangement of the chips and which prevent the interconnection lines related to the chips located at the periphery from being in a floating state.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: September 20, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Toshiaki Murao, Takeo Kikuchi, Toshihiko Iryu, Hidenori Nomura, Hiroyuki Sugamoto
  • Patent number: 5032889
    Abstract: A wafer-scale integrated circuit includes a plurality of functional blocks, a plurality of respectively corresponding connection terminals being provided in each of the functional blocks. Respectively corresponding pluralities of layered wirings and bonding wires interconnect predetermined, respective ones of said corresponding connection terminals in parallel for supplying power source and other voltages in common to the plurality of functional blocks. The parallel interconnections by the layered wirings and bonding wires, due to different, respective failure modes, affording increased reliability.
    Type: Grant
    Filed: September 20, 1990
    Date of Patent: July 16, 1991
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Murao, Takeo Kikuchi, Toshihiko Iryu, Hiroyuki Sugamoto, Hidenori Nomura