Abstract: A cooling device includes a first cooling section, a second cooling section, a first pump section, a second pump section, a branch section, a first flow path section, a second flow path section, a merging section, and a connection section. The branch section branches a refrigerant into two. The first flow path section connects the first cooling section and the first pump section, and one portion of the refrigerant passes through the first flow path section. The second flow path section connects the second cooling section and the second pump section, and another portion of the refrigerant passes through the second flow path section. The merging section merges the refrigerant having passed through each of the first flow path section and the second flow path section. The connection section connects the first and second flow path sections between the branch section and the merging section.

Abstract: A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability.

Abstract: A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability.

Abstract: An electronic-component mounting package includes: an insulating wiring laminate including an upper surface; differential lines located on the wiring laminate; differential lines located on the upper surface and alongside the differential lines and having shorter line lengths than the differential lines; and a wall covering part of each of the differential lines and being in contact with the upper surface of the wiring laminate. The wall includes a protruding portion in plan view from above the upper surface, and portions of the differential lines, the portions being covered with the protruding portion, are longer than portions of the differential lines, the portions being covered with the protruding portion.

Abstract: A dielectric substrate has a first surface including a first terminal joint and a second terminal joint arranged along a first side surface. A first lead terminal is bonded to the first terminal joint with a bond. A second lead terminal is bonded to the second terminal joint with a bond. The first lead terminal includes a first base bonded to the first terminal joint and a first lead extending from the first base. The second lead terminal includes a second base bonded to the second terminal joint and a second lead extending from the second base. The first lead terminal includes the first base having a larger thickness than the first lead.

Abstract: In an embodiment of the present disclosure, a wiring base includes an insulative base, a signal conductor, a first lead terminal, a first ground conductor, and a second lead terminal. The insulative base includes a first face and a second face. The signal conductor is provided on the first face. The first lead terminal is provided on the signal conductor. The first lead terminal extends in a first direction and includes a portion projecting from the insulative base in plan view toward the first face. The first ground conductor is provided on the second face. The second lead terminal is provided on the first ground conductor. At least a part of the second lead terminal overlaps the first lead terminal in the plan view toward the first face.

Abstract: A dielectric substrate has a first surface including a first terminal joint and a second terminal joint arranged along a first side surface. A first lead terminal is bonded to the first terminal joint with a bond. A second lead terminal is bonded to the second terminal joint with a bond. The first lead terminal includes a first base bonded to the first terminal joint and a first lead extending from the first base. The second lead terminal includes a second base bonded to the second terminal joint and a second lead extending from the second base. The first lead terminal includes the first base having a larger thickness than the first lead.

Abstract: A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability.

Abstract: A wiring board that includes a first dielectric layer having a rectangular plate form, a ground conductor wiring, a pair of signal conductor wirings, a ground conductor layer, and a second dielectric layer having a rectangular plate form. The ground conductor wiring is positioned on a first face of the first dielectric layer. The pair of signal conductor wirings carrying out signal transmission is positioned on the first face of the first dielectric layer. The ground conductor layer is positioned on a second face of the first dielectric layer. A first end portion of the signal conductor wiring extends to a first side of the first face. The region of the ground conductor layer where the first end portion of the signal conductor wiring is positioned in plan view is cut away inwardly from a first side of the second face opposing the first side of the first face.

Abstract: A wiring board includes a signal conductor wiring positioned on a first face of a first dielectric layer, and a ground conductor wiring positioned on a second face thereof. A region of the ground conductor wiring where a first end portion of the signal conductor wiring is positioned in plan view is cut away inwardly from a first side of the second face opposing a first side of the first face.

Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.

Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.

Abstract: A solid-state imaging device, includes: a substrate where a region of a first conductivity type is formed on at least a portion of a surface thereof; a region of a second conductivity type formed on at least a portion of a surface of the region of the first conductivity type; a multilayer wiring layer formed on the substrate; and a layer of the second conductivity type formed directly above the region of the second conductivity type in the multilayer wiring layer, connected to the region of the second conductivity type. A concentration of impurities in the layer of the second conductivity type is lower with decreasing proximity to the region of the second conductivity type.

Abstract: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An empty space is formed between a side wall of the trench and a side surface of the light guiding member. The side surface of the light guiding member is curved so that a central part of the side surface along a vertical direction is closer to a center axis of the trench than both end parts of the side surface along the vertical direction.

Abstract: A solid-state imaging device, includes: a substrate where a region of a first conductivity type is formed on at least a portion of a surface thereof; a region of a second conductivity type formed on at least a portion of a surface of the region of the first conductivity type; a multilayer wiring layer formed on the substrate; and a layer of the second conductivity type formed directly above the region of the second conductivity type in the multilayer wiring layer, connected to the region of the second conductivity type. A concentration of impurities in the layer of the second conductivity type is lower with decreasing proximity to the region of the second conductivity type.

Abstract: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An empty space is formed between a side wall of the trench and a side surface of the light guiding member. The side surface of the light guiding member is curved so that a central part of the side surface along a vertical direction is closer to a center axis of the trench than both end parts of the side surface along the vertical direction.

Abstract: A solid-state imaging device includes: a semiconductor substrate; and a signal processing section provided on a backside of the semiconductor substrate. The semiconductor substrate has; a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion section formed in a surface portion of the semiconductor substrate; a second impurity region of the first conductivity type formed below the first impurity region; and a first gate electrode penetrating the semiconductor substrate in a thickness direction of the semiconductor substrate, the first gate electrode transferring the signal charge stored in the first impurity region to the second impurity region. The signal processing section receives the signal charge transferred to the second impurity region.

Abstract: A CMP apparatus is used to subject a target surface of a semiconductor wafer to a polishing treatment, by moving the target surface and a polishing surface of a polishing cloth relative to each other while supplying a polishing liquid between the target surface and the polishing surface. Electric resistance is measured between pairs of measuring points arranged on opposite sides of dicing lines on the target surface, while subjecting the target surface to the polishing treatment. The polishing treatment is caused to be ended by comparing detected values of a changing rate in measured values of the electric property with a reference value set to correspond to an end point of the polishing treatment.