Patents by Inventor Toshihiko Kitamura

Toshihiko Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11946491
    Abstract: A liquid feeder includes a pump which is prevented from idling, and a replenisher including a cylinder that is a bottomed tube including an opening on a side adjacent to a communication flow path, the opening being connected to the communication flow path, and that is capable of accommodating a liquid in at least a portion of the cylinder, a seal that is housed in the cylinder in a movable manner along the cylinder, and seals the liquid in the cylinder, and a pressurizer to pressurize the seal toward a pump chamber.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 2, 2024
    Assignee: NIDEC CORPORATION
    Inventors: Toshihiko Tokeshi, Takahiro Imanishi, Yoshihisa Kitamura, Takehito Tamaoka
  • Patent number: 11889618
    Abstract: A dielectric substrate has a first surface including a first terminal joint and a second terminal joint arranged along a first side surface. A first lead terminal is bonded to the first terminal joint with a bond. A second lead terminal is bonded to the second terminal joint with a bond. The first lead terminal includes a first base bonded to the first terminal joint and a first lead extending from the first base. The second lead terminal includes a second base bonded to the second terminal joint and a second lead extending from the second base. The first lead terminal includes the first base having a larger thickness than the first lead.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 30, 2024
    Assignee: KYOCERA Corporation
    Inventor: Toshihiko Kitamura
  • Publication number: 20230057427
    Abstract: In an embodiment of the present disclosure, a wiring base includes an insulative base, a signal conductor, a first lead terminal, a first ground conductor, and a second lead terminal. The insulative base includes a first face and a second face. The signal conductor is provided on the first face. The first lead terminal is provided on the signal conductor. The first lead terminal extends in a first direction and includes a portion projecting from the insulative base in plan view toward the first face. The first ground conductor is provided on the second face. The second lead terminal is provided on the first ground conductor. At least a part of the second lead terminal overlaps the first lead terminal in the plan view toward the first face.
    Type: Application
    Filed: January 14, 2021
    Publication date: February 23, 2023
    Applicant: KYOCERA Corporation
    Inventors: Toshihiko KITAMURA, Takeo SATAKE
  • Publication number: 20220217834
    Abstract: A dielectric substrate has a first surface including a first terminal joint and a second terminal joint arranged along a first side surface. A first lead terminal is bonded to the first terminal joint with a bond. A second lead terminal is bonded to the second terminal joint with a bond. The first lead terminal includes a first base bonded to the first terminal joint and a first lead extending from the first base. The second lead terminal includes a second base bonded to the second terminal joint and a second lead extending from the second base. The first lead terminal includes the first base having a larger thickness than the first lead.
    Type: Application
    Filed: April 27, 2020
    Publication date: July 7, 2022
    Applicant: KYOCERA Corporation
    Inventor: Toshihiko KITAMURA
  • Publication number: 20220165889
    Abstract: A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability.
    Type: Application
    Filed: March 9, 2020
    Publication date: May 26, 2022
    Applicant: KYOCERA Corporation
    Inventor: Toshihiko KITAMURA
  • Patent number: 10512155
    Abstract: A wiring board that includes a first dielectric layer having a rectangular plate form, a ground conductor wiring, a pair of signal conductor wirings, a ground conductor layer, and a second dielectric layer having a rectangular plate form. The ground conductor wiring is positioned on a first face of the first dielectric layer. The pair of signal conductor wirings carrying out signal transmission is positioned on the first face of the first dielectric layer. The ground conductor layer is positioned on a second face of the first dielectric layer. A first end portion of the signal conductor wiring extends to a first side of the first face. The region of the ground conductor layer where the first end portion of the signal conductor wiring is positioned in plan view is cut away inwardly from a first side of the second face opposing the first side of the first face.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 17, 2019
    Assignee: KYOCERA Corporation
    Inventor: Toshihiko Kitamura
  • Publication number: 20180352648
    Abstract: A wiring board includes a signal conductor wiring positioned on a first face of a first dielectric layer, and a ground conductor wiring positioned on a second face thereof. A region of the ground conductor wiring where a first end portion of the signal conductor wiring is positioned in plan view is cut away inwardly from a first side of the second face opposing a first side of the first face.
    Type: Application
    Filed: January 26, 2017
    Publication date: December 6, 2018
    Applicant: KYOCERA Corporation
    Inventor: Toshihiko KITAMURA
  • Patent number: 9443777
    Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 13, 2016
    Assignee: KYOCERA CORPORATION
    Inventors: Mahiro Tsujino, Toshihiko Kitamura
  • Publication number: 20150130043
    Abstract: A semiconductor element housing package includes a rectangular ceramic package having a recess section on an upper surface thereof or a penetration section from the upper surface to a lower surface thereof, and a heat radiation plate attached to the lower surface of the ceramic package, extending from one side toward the other side of the lower surface up to a region in which the heat radiation plate overlays the recess section or the penetration section, which plate has a width on a side of the other side which is narrower than that on a side of one side. The package includes a plurality of first lead pins disposed on the lower surface of the ceramic package along the other side, and a pair of second lead pins disposed on the lower surface of the ceramic package on both sides of a narrow portion of the heat radiation plate.
    Type: Application
    Filed: May 16, 2013
    Publication date: May 14, 2015
    Applicant: KYOCERA Corporation
    Inventors: Mahiro Tsujino, Toshihiko Kitamura
  • Patent number: 7550792
    Abstract: A solid-state imaging device, includes: a substrate where a region of a first conductivity type is formed on at least a portion of a surface thereof; a region of a second conductivity type formed on at least a portion of a surface of the region of the first conductivity type; a multilayer wiring layer formed on the substrate; and a layer of the second conductivity type formed directly above the region of the second conductivity type in the multilayer wiring layer, connected to the region of the second conductivity type. A concentration of impurities in the layer of the second conductivity type is lower with decreasing proximity to the region of the second conductivity type.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: June 23, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Ogawa, Takashi Doi, Toshihiko Kitamura
  • Patent number: 7432530
    Abstract: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An empty space is formed between a side wall of the trench and a side surface of the light guiding member. The side surface of the light guiding member is curved so that a central part of the side surface along a vertical direction is closer to a center axis of the trench than both end parts of the side surface along the vertical direction.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: October 7, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Yamashita, Toshihiko Kitamura, Takashi Doi, Masaaki Ogawa, Takayuki Sakai
  • Publication number: 20080210985
    Abstract: A solid-state imaging device, includes: a substrate where a region of a first conductivity type is formed on at least a portion of a surface thereof; a region of a second conductivity type formed on at least a portion of a surface of the region of the first conductivity type; a multilayer wiring layer formed on the substrate; and a layer of the second conductivity type formed directly above the region of the second conductivity type in the multilayer wiring layer, connected to the region of the second conductivity type. A concentration of impurities in the layer of the second conductivity type is lower with decreasing proximity to the region of the second conductivity type.
    Type: Application
    Filed: July 16, 2007
    Publication date: September 4, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Ogawa, Takashi Doi, Toshihiko Kitamura
  • Publication number: 20070275496
    Abstract: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An empty space is formed between a side wall of the trench and a side surface of the light guiding member. The side surface of the light guiding member is curved so that a central part of the side surface along a vertical direction is closer to a center axis of the trench than both end parts of the side surface along the vertical direction.
    Type: Application
    Filed: May 22, 2007
    Publication date: November 29, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsuko Yamashita, Toshihiko Kitamura, Takashi Doi, Masaaki Ogawa, Takayuki Sakai
  • Publication number: 20070052056
    Abstract: A solid-state imaging device includes: a semiconductor substrate; and a signal processing section provided on a backside of the semiconductor substrate. The semiconductor substrate has; a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion section formed in a surface portion of the semiconductor substrate; a second impurity region of the first conductivity type formed below the first impurity region; and a first gate electrode penetrating the semiconductor substrate in a thickness direction of the semiconductor substrate, the first gate electrode transferring the signal charge stored in the first impurity region to the second impurity region. The signal processing section receives the signal charge transferred to the second impurity region.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi Doi, Toshihiko Kitamura, Takayuki Sakai
  • Patent number: 6015754
    Abstract: A CMP apparatus is used to subject a target surface of a semiconductor wafer to a polishing treatment, by moving the target surface and a polishing surface of a polishing cloth relative to each other while supplying a polishing liquid between the target surface and the polishing surface. Electric resistance is measured between pairs of measuring points arranged on opposite sides of dicing lines on the target surface, while subjecting the target surface to the polishing treatment. The polishing treatment is caused to be ended by comparing detected values of a changing rate in measured values of the electric property with a reference value set to correspond to an end point of the polishing treatment.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: January 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasukazu Mase, Yoshitaka Matsui, Takeshi Kubota, Toshihiko Kitamura