Patents by Inventor Toshihiko Mitani

Toshihiko Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4109101
    Abstract: A novel modulator converts a sequence of N'ary codes representative of an element P of a set (0, 1, 2, . . . , N - 1) into a sequence of 2N-phase carrier pulses, where N = 2.sup.n, n being a positive integer. A phase shift in the carrier signal between each carrier pulse and the next preceding one is selected from P.pi./N and (P + N).pi./N in compliance with a prescribed law of correlation between the N'ary codes in the sequence. Alternatively, the carrier signal is given in each carrier pulse a phase selected in the manner specified. For convenience of resorting to the prescribed correlation law, the N'ary code sequence may be converted into N trains, corresponding to the respective elements P, of three-level signals, 0 and .+-.1. In the train corresponding to a particular element, the three-level signals are successively produced with the prescribed correlation law, such as with resort to a bipolar or duobinary technique.
    Type: Grant
    Filed: June 2, 1976
    Date of Patent: August 22, 1978
    Assignee: Nippon Electric Company, Ltd.
    Inventor: Toshihiko Mitani
  • Patent number: 4015205
    Abstract: A baseband signal switching arrangement for diversity reception in a PCM communication system is disclosed. The switching arrangement is characterized by the provision of a 1/n write-in frequency-dividing counter in each receiving channel to count clock signals in response to being reset by a frame signal and n buffer memory circuits for successively writing bit information of a received digital signal in response to the n frequency-divided outputs of the 1/n frequency-dividing counter. The switching arrangement further includes a 1/n read-out frequency-dividing counter which is adapted to successively read out memory outputs of one set of the n buffer memory circuits and a switching means for enabling the 1/n read-out frequency-dividing counter to selectively read out memory outputs of a given set of buffer memory circuits.
    Type: Grant
    Filed: February 17, 1976
    Date of Patent: March 29, 1977
    Assignee: Nippon Electric Company, Ltd.
    Inventors: Kiyoshi Ikeda, Toshihiko Mitani