Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.

Abstract: A variety of applications can include apparatus having p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors with different metal silicide contacts. The active area of the NMOS transistor can include a first metal silicide having a first metal element, where the first metal silicide is a vertical lowest portion of a contact for the NMOS. The PMOS transistor can include a stressor source/drain region to a channel region of the PMOS transistor and a second metal silicide directly contacting the stressor source/drain region without containing the first metal element. The process flow to form the PMOS and NMOS transistors can enable making simultaneous contacts by a pre-silicide in the active area of the NMOS transistor, without affecting stressor source/drain regions in the PMOS transistor. The process flow and resulting structures for PMOS transistors and NMOS transistors can be used in various integrated circuits and devices.

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include silicide contacts on source/drain regions in different conductivity type transistors. In one example, silicide contacts are different between transistors of different conductivity types.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include transistors formed in a (100) surface of a semiconductor substrate wherein a channel is oriented in a <100> direction. The transistors further include one or more strain induced dislocations adjacent to a channel.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include semiconductor devices having two or more fins, the fins separated by one or more inter-fin trenches. An isolation structure is included adjacent to the two or more fins, the isolation structure having a depth greater than the inter-fin trench depth.

Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.

Abstract: DRAM circuitry comprises a memory array comprising memory cells individually comprising a transistor and a charge-storage device. The transistors individually comprise two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array. One of the source/drain regions is electrically coupled to one of the charge-storage devices. The other of the source/drain regions is electrically coupled to one of multiple sense lines of the memory array. Peripheral circuitry comprises wordline-driver transistors having gates which individually comprise one of the wordlines and comprises sense-line-amplifier transistors having gates which individually comprise one of the sense lines. The sense-line-amplifier transistors and the wordline-driver transistors individually are a finFET having at least one fin comprising a channel region of the respective finFET.

Abstract: Embodiments disclosed herein include CMOS image sensors and methods of forming such devices. In an embodiment, a method of forming a CMOS image sensor comprises pressurizing a chamber with a gas comprising hydrogen, and annealing a substrate in the pressurized chamber. In an embodiment the substrate comprises the CMOS image sensor. In an embodiment, the CMOS image sensor comprises a semiconductor body and a trench around a perimeter the semiconductor body, wherein the trench is filled with a high-k oxide that directly contacts the semiconductor body. In an embodiment, the method further comprises, depressurizing the chamber.

Abstract: The present invention includes, in addition to transistors each (Mm,n) provided at the intersection of a gate bus line (GLn) with a data bus line (DLm): block potential applying transistors (DMn) connected to respective ends of gate bus lines (GLn) which ends are not connected to a gate driver (11); a potential supply line (VLL) connected to the gate bus lines (GLn) via the block potential applying transistors (DMn); and a blocking signal supplying section (131) for, immediately after the gate driver (11) supplies a first conduction signal for bringing the transistors (Mm,n) into conduction, supplying to the block potential applying transistors (DMn), a second conduction signal for bringing the block potential applying transistors (DMn) into conduction.

Abstract: A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.

Abstract: A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.

Abstract: A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.

Abstract: In one embodiment of the present application, a display is disclosed in which any defective pixel is rendered less noticeable even if a full-screen white display or suchlike is effected. In a normally-white liquid crystal display device, which transitions after power activation from non-display state through display starting state, where a full-screen blank white display is effected, to normal display state, an auxiliary electrode driver portion controls an auxiliary capacitance line voltage Vcs to be applied to auxiliary capacitance lines in accordance with the state of the liquid crystal display device in the following manner.

Abstract: The present invention includes, in addition to transistors each (Mm,n) provided at the intersection of a gate bus line (GLn) with a data bus line (DLm): block potential applying transistors (DMn) connected to respective ends of gate bus lines (GLn) which ends are not connected to a gate driver (11); a potential supply line (VLL) connected to the gate bus lines (GLn) via the block potential applying transistors (DMn); and a blocking signal supplying section (131) for, immediately after the gate driver (11) supplies a first conduction signal for bringing the transistors (Mm,n) into conduction, supplying to the block potential applying transistors (DMn), a second conduction signal for bringing the block potential applying transistors (DMn) into conduction.

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to the source edge of the channel region than to the drain edge of the channel region.

Abstract: A drive order control circuit 14 generates a drive order control signal LR so as to change periodically, such as every frame time or every line time. Based on the drive order control signal LR, a data signal line drive circuit 3 switches between driving data signal lines S1 to Sm in the left-to-right direction in accordance with the disposition order, and driving them in the right-to-left direction in accordance with the disposition order. A memory control circuit 15 switches the order of reading digital video signals Vd from a frame memory 12 in units of one or more lines in accordance with the drive order control signal LR. By changing the order of driving the data signal lines, it becomes possible to disperse any ghost generated on the display screen in the temporal and/or spatial directions, thereby reducing the visibility of the ghost.

Abstract: A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.

Abstract: A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front gate region formed on a gate insulating film formed on one of side surfaces of the semiconductor region such that the source region and the drain region are separated from each other by the front gate region, and a back gate region formed on a gate insulating film formed on an opposite side surface of the semiconductor region such that the source region and the drain region are separated from each other by the back gate region. Each memory cell shares the back gate region with a memory cell adjacent in a row direction.

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to the source edge of the channel region than to the drain edge of the channel region.

Abstract: The present invention relates to a display device and an electronic device provided with same. An object of the present invention is to improve an electrostatic withstand voltage of the display device, thereby suppressing breakage of an electric circuit formed in a panel due to static electricity. An intra-panel protective circuit (120) is provided between an input/output terminal (300) of a liquid crystal panel (10) and an intra-panel electric circuit (110), and, an intra-LSI protective circuit (220) is provided between the input/output terminal (300) of the liquid crystal panel (10) and a liquid crystal controller (210) in an LSI (200). A signal line connecting the input/output terminal (300) with the intra-panel electric circuit (110) and a signal line connecting the input/output terminal (300) with the liquid crystal controller (210) are connected with two diodes, respectively.