Patents by Inventor Toshihiko Morita
Toshihiko Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7793197Abstract: One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.Type: GrantFiled: August 24, 2006Date of Patent: September 7, 2010Assignee: Fujitsu LimitedInventors: Toshio Ito, Toshihiko Morita
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Patent number: 7644337Abstract: An encoder divides the data in which sector data is adjacently connected to a first RS parity generated in Reed Solomon encoding into blocks to and subjects each of the blocks to cyclic Hamming encoding so as to generate Hamming parities. Subsequently, the data in which the Hamming parities are aligned in a row is subjected to Reed Solomon encoding so as to generate a second RS parity, and encoded data in which the first RS parity and the second RS parity are adjacently connected to the sector data is output. A decoder s divides the sector data and the first RS parity into n blockes and cyclic Hamming encoding, aligns the parities thereof, corrects errors in the parities by Reed Solomon decoding by the second RS parity, then corrects 1-bit errors in blockes by cyclic Hamming decoding, and further corrects errors of 2 or more bits by Reed Solomon decoding by the first RS parity.Type: GrantFiled: August 31, 2006Date of Patent: January 5, 2010Assignee: Fujitsu LimitedInventors: Toshio Ito, Toshihiko Morita
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Patent number: 7620873Abstract: An information sequence having a code length of N (N=K+M), where K is information length and M is parity length, is encoded into a code sequence by using an LDPC code. The LDPC code is generated based on a matrix H, with M rows and N columns. The matrix H includes a check matrix H2 and a check matrix H1 . The check matrix H2 has M rows and M columns, it is a cyclic permutation matrix, and an inverse matrix exists for the check matrix H2, and its column weight is 3. The check matrix H1 has M rows and K columns.Type: GrantFiled: March 21, 2006Date of Patent: November 17, 2009Assignee: Fujitsu LimitedInventors: Toshikazu Kanaoka, Toshihiko Morita
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Patent number: 7620882Abstract: A decoder decodes a code by selecting, based on a predetermined condition, a path out of paths representing a transition of each of states in a trellis diagram. A storing unit stores, when a path at time k is selected, information on a selection history of a path selected at time prior to time (k?(a constraint length of a code)+1). A path detecting unit detects a path to be excluded from a path selection candidate, based on the information stored in the storing unit and information on a state of a transition source when a state transition occurs from time k?1 to time k.Type: GrantFiled: March 30, 2006Date of Patent: November 17, 2009Assignee: Fujitsu LimitedInventors: Toshikazu Kanaoka, Toshihiko Morita
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Patent number: 7590929Abstract: A record reproduction apparatus includes an encoding unit that encodes sector data to be written into a recording medium, by dividing the data into a predetermined number of blocks, and an iterative decoding unit that iteratively decodes the sector data read from the recording medium, by dividing the sector data into the predetermined number of blocks.Type: GrantFiled: June 16, 2004Date of Patent: September 15, 2009Assignee: Fujitsu LimitedInventors: Toshihiko Morita, Mitsuhiko Ohta, Takao Sugawara
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Patent number: 7385533Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.Type: GrantFiled: July 10, 2006Date of Patent: June 10, 2008Assignee: Fujitsu LimitedInventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
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Publication number: 20070266300Abstract: An encoder divides the data in which sector data is adjacently connected to a first RS parity generated in Reed Solomon encoding into blocks to and subjects each of the blocks to cyclic Hamming encoding so as to generate Hamming parities. Subsequently, the data in which the Hamming parities are aligned in a row is subjected to Reed Solomon encoding so as to generate a second RS parity, and encoded data in which the first RS parity and the second RS parity are adjacently connected to the sector data is output. A decoder divides the sector data and the first RS parity into n blockes and cyclic Hamming encoding, aligns the parities thereof, corrects errors in the parities by Reed Solomon decoding by the second RS parity, then corrects 1-bit errors in blockes by cyclic Hamming decoding, and further corrects errors of 2 or more bits by Reed Solomon decoding by the first RS parity.Type: ApplicationFiled: August 31, 2006Publication date: November 15, 2007Inventors: Toshio Ito, Toshihiko Morita
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Publication number: 20070245220Abstract: One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.Type: ApplicationFiled: August 24, 2006Publication date: October 18, 2007Inventors: Toshio Ito, Toshihiko Morita
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Patent number: 7248188Abstract: An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.Type: GrantFiled: March 16, 2006Date of Patent: July 24, 2007Assignee: Fujitsu LimitedInventors: Toshio Ito, Masaru Sawada, Toshihiko Morita
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Publication number: 20070168843Abstract: A decoder decodes a code by selecting, based on a predetermined condition, a path out of paths representing a transition of each of states in a trellis diagram. A storing unit stores, when a path at time k is selected, information on a selection history of a path selected at time prior to time (k?(a constraint length of a code)+1). A path detecting unit detects a path to be excluded from a path selection candidate, based on the information stored in the storing unit and information on a state of a transition source when a state transition occurs from time k?1 to time k.Type: ApplicationFiled: March 30, 2006Publication date: July 19, 2007Inventors: Toshikazu Kanaoka, Toshihiko Morita
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Patent number: 7237173Abstract: A recording and reproducing apparatus having an ECC-less error correction function, includes an erasure detector generating an erasure flag indicating erasure of a read signal; and an iterative decoder having two soft-in/soft-out (SISO) decoders, i.e., an inner decoder and an outer decoder, and correcting the erasure by inputting the erasure flag ek into the inner decoder and performing erasure compensation in the inner decoder. As the erasure compensation in the inner decoder, channel information is masked while the erasure flag is on. The erasure of data due to a media defect is detected inside the iterative decoder, and the second erasure flag is inputted into the inner decoder to perform erasure compensation in the inner decoder.Type: GrantFiled: June 3, 2002Date of Patent: June 26, 2007Assignee: Fujitsu LimitedInventors: Toshihiko Morita, Yuichi Sato, Takao Sugawara
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Publication number: 20070143657Abstract: An information sequence having a code length of N (N=K+M), where K is information length and M is parity length, is encoded into a code sequence by using an LDPC code. The LDPC code is generated based on a matrix H, with M rows and N columns. The matrix H includes a check matrix H2 and a check matrix H1. The check matrix H2 has M rows and M columns, it is a cyclic permutation matrix, and an inverse matrix exists for the check matrix H2, and its column weight is 3. The check matrix H1 has M rows and K columns.Type: ApplicationFiled: March 21, 2006Publication date: June 21, 2007Inventors: Toshikazu Kanaoka, Toshihiko Morita
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Patent number: 7138931Abstract: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.Type: GrantFiled: November 5, 2004Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventors: Toshio Ito, Masaru Sawada, Toshihiko Morita, Takao Sugawara
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Publication number: 20060250286Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.Type: ApplicationFiled: July 10, 2006Publication date: November 9, 2006Inventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
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Publication number: 20060220928Abstract: An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.Type: ApplicationFiled: March 16, 2006Publication date: October 5, 2006Inventors: Toshio Ito, Masaru Sawada, Toshihiko Morita
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Publication number: 20060220926Abstract: An encoder includes an encoded-bit-string generating unit that generates a plurality of bit strings encoded by scrambling with respect to an input bit string; a DC-component evaluating unit that selects a bit string having a predetermined width in the bit strings generated by the encoded-bit-string generating unit, while shifting bits one by one or every m-bits, where m is a positive integer, and evaluates the DC component in each of the bit strings selected; and a bit-string extracting unit that extracts a bit string with suppressed DC component from among the bit strings encoded, based on a result of an evaluation by the direct-current-component evaluating unit.Type: ApplicationFiled: August 11, 2005Publication date: October 5, 2006Inventors: Toshio Ito, Masaru Sawada, Toshihiko Morita
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Patent number: 7098818Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.Type: GrantFiled: June 24, 2005Date of Patent: August 29, 2006Assignee: Fujitsu LimitedInventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
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Patent number: 7035029Abstract: An information recording/reading apparatus employs a preamble to reproduce a clock used when recording information in a recording medium and reads the information out of the recording medium at a timing synchronized with a read signal. The preamble is split and recorded by replacing a middle portion of the preamble with data and a sync byte. While a first buffer is employed to delay signal data read out of the recording medium, a frequency offset detector detects a frequency offset using the split preamble.Type: GrantFiled: February 11, 2004Date of Patent: April 25, 2006Assignee: Fujitsu LimitedInventors: Masaru Sawada, Toshihiko Morita, Takao Sugawara
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Patent number: 7031090Abstract: In a Maximum A posteriori Probability decoding (MAP decoding), a correlation and a deviation of noises for past and future states which depend on input signal patterns in past N bits and future Q bits are calculated by training by a noise correlation arithmetic operating unit 84 and they are stored. Upon reproduction, in a white noise arithmetic operating unit 91, white noise values for the past and future states in which colored noises are converted into white noises are obtained by using the stored correlation and deviation of the noises. In an input signal arithmetic operating unit 92, an input signal (channel information) ?c(yk|Smk) of the MAP decoding is calculated from the white noise values and the deviation for the past and future states. A likelihood in the MAP decoding is obtained from the input signal.Type: GrantFiled: October 29, 2001Date of Patent: April 18, 2006Assignee: Fujitsu LimitedInventors: Kazuhito Ichihara, Takao Sugawara, Yuichi Sato, Toshihiko Morita, Motomu Takatsu
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Publication number: 20050225458Abstract: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.Type: ApplicationFiled: November 5, 2004Publication date: October 13, 2005Inventors: Toshio Ito, Masaru Sawada, Toshihiko Morita, Takao Sugawara