Patents by Inventor Toshihiko Ochiai

Toshihiko Ochiai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200406708
    Abstract: A vehicle compartment temperature control device includes: a first interior member including a temperature control mechanism layer that can adjust the temperature of a leg of the occupant in a first region, that is, a front portion and the like. The vehicle compartment temperature control device also includes a second interior member disposed above the first interior member and including a temperature control mechanism layer in a second region, that is, a steering and the like that can adjust the temperature of a part above the leg and is different from the temperature control mechanism layer in the first region. The vehicle compartment temperature control device also includes an ECU. The ECU performs control such that the temperature of the temperature control mechanism layer in the first region is higher than the temperature of the temperature control mechanism layer in the second region.
    Type: Application
    Filed: February 26, 2019
    Publication date: December 31, 2020
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Kazuya YOKOTA, Hiroya OCHIAI, Toshihiko OHSUMI, Junji KANEISHI, Tomohiro YOSHIZUE, Toshihiro KASHIMA
  • Publication number: 20200173011
    Abstract: There are provided a vapor deposition mask capable of satisfying both high definition and lightweight in upsizing and forming a vapor deposition pattern with high definition while securing strength, a vapor deposition mask preparation body capable of simply producing the vapor deposition mask and a method for producing a vapor deposition mask, and furthermore, a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition. A metal mask 10 in which a slit 15 is provided and a resin mask 20 in which openings 25 corresponding to a pattern to be produced by vapor deposition are provided at a position of overlapping with the slit 15 are stacked, and the metal mask 10 has a general region 10a in which the slit 15 is provided and a thick region 10b larger in thickness than the general region.
    Type: Application
    Filed: February 11, 2020
    Publication date: June 4, 2020
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari OBATA, Toshihiko TAKEDA, Hiroshi KAWASAKI, Hiroyuki NISHIMURA, Atsushi MAKI, Hiromitsu OCHIAI, Yoshinori HIROBE
  • Patent number: 10597766
    Abstract: There are provided a vapor deposition mask capable of satisfying both high definition and lightweight in upsizing and forming a vapor deposition pattern with high definition while securing strength, a vapor deposition mask preparation body capable of simply producing the vapor deposition mask and a method for producing a vapor deposition mask, and furthermore, a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition. A metal mask 10 in which a slit 15 is provided and a resin mask 20 in which openings 25 corresponding to a pattern to be produced by vapor deposition are provided at a position of overlapping with the slit 15 are stacked, and the metal mask 10 has a general region 10a in which the slit 15 is provided and a thick region 10b larger in thickness than the general region.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: March 24, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari Obata, Toshihiko Takeda, Hiroshi Kawasaki, Hiroyuki Nishimura, Atsushi Maki, Hiromitsu Ochiai, Yoshinori Hirobe
  • Patent number: 10597768
    Abstract: There are provided a vapor deposition mask capable of satisfying both high definition and lightweight in upsizing and forming a vapor deposition pattern with high definition while securing strength, a vapor deposition mask preparation body capable of simply producing the vapor deposition mask and a method for producing a vapor deposition mask, and furthermore, a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition. A metal mask 10 in which a slit 15 is provided and a resin mask 20 in which openings 25 corresponding to a pattern to be produced by vapor deposition are provided at a position of overlapping with the slit 15 are stacked, and the metal mask 10 has a general region 10a in which the slit 15 is provided and a thick region 10b larger in thickness than the general region.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 24, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari Obata, Toshihiko Takeda, Hiroshi Kawasaki, Hiroyuki Nishimura, Atsushi Maki, Hiromitsu Ochiai, Yoshinori Hirobe
  • Patent number: 10347552
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 9, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuichi Oikawa, Toshihiko Ochiai, Shuuichi Kariyazaki, Yuji Kayashima, Tsuyoshi Kida
  • Patent number: 10062655
    Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 28, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Toshihiko Ochiai
  • Patent number: 10026700
    Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Toshihiko Ochiai
  • Publication number: 20180151460
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Application
    Filed: January 25, 2018
    Publication date: May 31, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Ryuichi OIKAWA, Toshihiko OCHIAI, Shuuichi KARIYAZAKI, Yuji KAYASHIMA, Tsuyoshi KIDA
  • Patent number: 9917026
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuichi Oikawa, Toshihiko Ochiai, Shuuichi Kariyazaki, Yuji Kayashima, Tsuyoshi Kida
  • Publication number: 20170236789
    Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventor: Toshihiko OCHIAI
  • Publication number: 20170213776
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Application
    Filed: December 24, 2014
    Publication date: July 27, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Ryuichi OIKAWA, Toshihiko OCHIAI, Shuuichi KARIYAZAKI, Yuji KAYASHIMA, Tsuyoshi KIDA
  • Patent number: 9673153
    Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: June 6, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshihiko Ochiai
  • Patent number: 9274474
    Abstract: The fixing device includes a rotary member for contacting the unfixed toner image, a pressure member for forming the nip portion by contacting the rotary member, and a cover for covering the rotary member with a space between the rotary member and the cover. In a cross section of the fixing device, the cross section being orthogonal to a generatrix direction of the rotary member, the shortest distance (H) between the nip portion and a farthest surface portion of the rotary member farthest away from a surface portion forming the nip portion of the rotary member, the maximum width (W) of the rotary member in the conveyance direction of the recording member, and an area (S) of the space in a range of the maximum width W in the cross section satisfy with a relationship of S/W?0.7×H.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: March 1, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahito Omata, Shoichiro Ikegami, Masahiko Suzumi, Terutaka Endo, Takeshi Niimura, Takehiko Suzuki, Toshihiko Ochiai
  • Publication number: 20150086253
    Abstract: The fixing device includes a rotary member for contacting the unfixed toner image, a pressure member for forming the nip portion by contacting the rotary member, and a cover for covering the rotary member with a space between the rotary member and the cover, wherein in a cross section of the fixing device, the cross section being orthogonal to a generatrix direction of the rotary member, wherein a shortest distance (H) between the nip portion and a farthest surface portion of the rotary member farthest away from a surface portion forming the nip portion of the rotary member, a maximum width (W) of the rotary member in the conveyance direction of the recording member, and an area (S) of the space in a range of the maximum width W in the cross section satisfy with a relationship of S/W?0.7×H.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 26, 2015
    Inventors: Masahito Omata, Shoichiro Ikegami, Masahiko Suzumi, Terutaka Endo, Takeshi Niimura, Takehiko Suzuki, Toshihiko Ochiai
  • Publication number: 20140167286
    Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.
    Type: Application
    Filed: November 12, 2013
    Publication date: June 19, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshihiko OCHIAI
  • Patent number: 8618579
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroharu Shimizu, Masakazu Nishibori, Toshihiko Ochiai
  • Patent number: 8354697
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroharu Shimizu, Masakazu Nishibori, Toshihiko Ochiai
  • Publication number: 20120007189
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Inventors: HIROHARU SHIMIZU, Masakazu Nishibori, Toshihiko Ochiai
  • Patent number: 8043900
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Grant
    Filed: August 23, 2009
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroharu Shimizu, Masakazu Nishibori, Toshihiko Ochiai
  • Publication number: 20100059794
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Application
    Filed: August 23, 2009
    Publication date: March 11, 2010
    Inventors: Hiroharu SHIMIZU, Masakazu Nishibori, Toshihiko Ochiai