Abstract: A vector processor for executing vector instructions comprises a plurality of vector registers and a plurality of pipeline arithmetic logic units. The vector registers are constructed with a circuit which operates in a speed equal to 2n times as fast as the processing speed of the pipeline arithmetic logic units. Either the read or the write operation from or to the vector registers are carried out in the time obtained by a processing cycle of each of the pipeline arithmetic logic units multiplied by n/2.

Abstract: A general purpose data processing apparatus is provided which is adapted also for processing vector instructions. An instruction control unit reads instructions out of a memory and decodes them. If the instructions are different from vector instructions, an arithmetic unit performs the instructed operations. If the instructions are vector instructions, the subsequent control is performed by a vector instruction control unit. The vector instruction control unit decodes the vector instructions and controls the vector operands to cause the same arithmetic unit to perform the vector operation in accordance with the vector operands. Thus, the general purpose data processing apparatus can process vector instructions at high speed.