Patents by Inventor Toshihiko Onozuka
Toshihiko Onozuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9390934Abstract: A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor device, capable of improving accuracy of a product and capable of shortening manufacturing time. In a method of manufacturing a diffraction grating by using a phase shift mask (in which a light shield part and a light transmission part are periodically arranged), light emitted from an illumination light source is transmitted through the phase shift mask, and a photoresist on a surface of a Si wafer is exposed by providing interference between zero diffraction order light and positive first diffraction order light which are generated by the transmission through this phase shift mask onto the surface of the Si wafer, and a diffraction grating which has a blazed cross-sectional shape is formed on the Si wafer.Type: GrantFiled: September 13, 2012Date of Patent: July 12, 2016Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Kazuyuki Kakuta, Toshihiko Onozuka, Shigeru Matsui, Yoshisada Ebata, Norio Hasegawa
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Publication number: 20140302679Abstract: A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor device, capable of improving accuracy of a product and capable of shortening manufacturing time. In a method of manufacturing a diffraction grating by using a phase shift mask (in which a light shield part and a light transmission part are periodically arranged), light emitted from an illumination light source is transmitted through the phase shift mask, and a photoresist on a surface of a Si wafer is exposed by providing interference between zero diffraction order light and positive first diffraction order light which are generated by the transmission through this phase shift mask onto the surface of the Si wafer, and a diffraction grating which has a blazed cross-sectional shape is formed on the Si wafer.Type: ApplicationFiled: September 13, 2012Publication date: October 9, 2014Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Kazuyuki Kakuta, Toshihiko Onozuka, Shigeru Matsui, Yoshisada Ebata, Norio Hasegawa
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Publication number: 20140092384Abstract: The present invention has been made in view of the above, and an object thereof is to provide a manufacturing technique capable of manufacturing a diffraction grating which is suitable for use in a spectrophotometer and has an apex angle of a convex portion of about 90° and can satisfy high diffraction efficiency and a low stray light amount. A method of manufacturing a diffraction grating, the method including: setting an exposure condition such that a sectional shape of a convex portion of a resist on a substrate, which has been formed by exposure, is an asymmetric triangle with respect to an opening portion shape of a mask having an opening portion with a periodic structure and an angle formed by a long side and a short side of the triangle is about 90°; and performing exposure.Type: ApplicationFiled: May 17, 2012Publication date: April 3, 2014Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Yoshisada Ebata, Shigeru Matsui, Norio Hasegawa, Kazuyuki Kakuta, Toshihiko Onozuka
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Patent number: 8586447Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: GrantFiled: July 3, 2012Date of Patent: November 19, 2013Assignee: Hitachi, Ltd.Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Publication number: 20130244146Abstract: After performing a pretreatment step of coating an organic solvent mixed with a polymeric organic compound over a substrate having a tungsten film formed on the surface of the substrate, a chemically amplified resist is coated to form a resist pattern. Further, a ratio of a C1s peak intensity to a W4d peak intensity measured by XPS is 0.1 or mote at the surface of the tungsten film after the pretreatment step and before coating the chemically amplified resist.Type: ApplicationFiled: February 4, 2013Publication date: September 19, 2013Applicant: HITACHI, LTD.Inventors: Kazuyuki Kakuta, Toshio Ando, Kenji Hiruma, Toshihiko Onozuka, Kiyomi Katsuyama, Kiyohiko Satoh, Yasushi IIDA
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Publication number: 20120270390Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: ApplicationFiled: July 3, 2012Publication date: October 25, 2012Applicant: Hitachi, Ltd.Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Patent number: 8247902Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: GrantFiled: February 15, 2011Date of Patent: August 21, 2012Assignee: Hitachi, Ltd.Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Publication number: 20110140275Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: ApplicationFiled: February 15, 2011Publication date: June 16, 2011Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Patent number: 7911055Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: GrantFiled: January 23, 2009Date of Patent: March 22, 2011Assignee: Hitachi, Ltd.Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Publication number: 20090142919Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: ApplicationFiled: January 23, 2009Publication date: June 4, 2009Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Patent number: 7501347Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: GrantFiled: June 5, 2006Date of Patent: March 10, 2009Assignee: Hitachi, Ltd.Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Publication number: 20060281298Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.Type: ApplicationFiled: June 5, 2006Publication date: December 14, 2006Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
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Patent number: 6040110Abstract: The present invention provides a process for the removal of a resist layer formed on a semiconductor substrate, which enables easy removal of a resist layer without causing any damage on a gate oxide layer, and an apparatus therefor. The process comprises the steps of forming a gate oxide layer on the semiconductor substrate; forming a resist layer as a resist pattern on the gate oxide layer; removing the gate oxide layer at unnecessary area utilizing the resist layer as a mask; applying a pressure-sensitive adhesive sheet to the semiconductor substrate such that the gate oxide layer left on the semiconductor substrate and the resist layer are masked, and peeling the pressure-sensitive adhesive sheet together with the resist layer off the semiconductor substrate to separate and remove the resist layer from the semiconductor substrate.Type: GrantFiled: August 6, 1998Date of Patent: March 21, 2000Assignee: Nitto Denko CorporationInventors: Seiichirou Shirai, Toshihiko Onozuka, Takayuki Noishiki, Satoshi Sakai, Katsuhiro Sasajima, Eiji Toyoda, Makoto Namikawa
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Patent number: 5725971Abstract: A technique to minimize an increase in the design and manufacture times required for making phase shift masks is provided. The process of the technique involves preparing a hole unit cell comprising one target hole and auxiliary holes located close to the four sides of the target hole, and then laying out on first layout data first hole unit cells 26c.sub.1 -26c.sub.3 arranged in a certain orientation at a first pitch and second hole unit cells 27c.sub.1 -27c.sub.3 arranged in the same orientation at a second pitch, narrower than the first pitch. This process generates data of hole groups, each comprising the target hole and auxiliary holes on a first phase shift mask that is used in forming hole patterns in a resist film coated over the semiconductor substrate.Type: GrantFiled: February 13, 1996Date of Patent: March 10, 1998Assignee: Hitachi, Ltd.Inventors: Noboru Moriuchi, Seiichirou Shirai, Toshihiko Onozuka