Patents by Inventor Toshihiko Usami

Toshihiko Usami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9470990
    Abstract: A storage to store a dispersion liquid in which particles including a resin are dispersed in a solvent is provided. The storage includes a storage tank to store the dispersion liquid, which is arranged on a passage leading from a dispersion liquid producing device to produce the dispersion liquid to a solvent removing device to remove the solvent from the dispersion liquid; and a pressure adjuster to adjust the pressure of the dispersion liquid in the storage tank to a pressure between the pressure of the dispersion liquid in the dispersion liquid producing device and the pressure of the dispersion liquid in the solvent removing device.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: October 18, 2016
    Assignee: Ricoh Company, Ltd.
    Inventors: Taro Araki, Masashi Miyakawa, Toshihiko Usami
  • Patent number: 9159706
    Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: October 13, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20150259123
    Abstract: A storage to store a dispersion liquid in which particles including a resin are dispersed in a solvent is provided. The storage includes a storage tank to store the dispersion liquid, which is arranged on a passage leading from a dispersion liquid producing device to produce the dispersion liquid to a solvent removing device to remove the solvent from the dispersion liquid; and a pressure adjuster to adjust the pressure of the dispersion liquid in the storage tank to a pressure between the pressure of the dispersion liquid in the dispersion liquid producing device and the pressure of the dispersion liquid in the solvent removing device.
    Type: Application
    Filed: February 23, 2015
    Publication date: September 17, 2015
    Inventors: Taro ARAKI, Masashi MIYAKAWA, Toshihiko USAMI
  • Patent number: 9087710
    Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: July 21, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Toshihiko Usami
  • Publication number: 20150001538
    Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.
    Type: Application
    Filed: September 17, 2014
    Publication date: January 1, 2015
    Inventors: Masachika Masuda, Toshihiko Usami
  • Patent number: 8853864
    Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: October 7, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20130328046
    Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.
    Type: Application
    Filed: July 25, 2013
    Publication date: December 12, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Masachika MASUDA, Toshihiko USAMI
  • Patent number: 8502395
    Abstract: A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 6, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20120211875
    Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 23, 2012
    Inventor: Toshihiko USAMI
  • Publication number: 20120168965
    Abstract: A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.
    Type: Application
    Filed: March 7, 2012
    Publication date: July 5, 2012
    Inventors: Masachika MASUDA, Toshihiko USAMI
  • Patent number: 8198718
    Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 12, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toshihiko Usami
  • Patent number: 8169089
    Abstract: A semiconductor device includes at least bonding wires between electrode pads on a main surface of a semiconductor chip and connection pads on a wiring board. The wires form loop shapes from the electrode pads of the semiconductor chip. The semiconductor device also includes at least forming flat parts on the loop-shaped wires, and using a sealing material to seal the semiconductor chip such as to bury the flat parts.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: May 1, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toshihiko Usami
  • Patent number: 8159062
    Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 17, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20120013027
    Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Masachika MASUDA, Toshihiko Usami
  • Patent number: 8067251
    Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: November 29, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20110195530
    Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.
    Type: Application
    Filed: December 30, 2010
    Publication date: August 11, 2011
    Inventors: Masachika Masuda, Toshihiko Usami
  • Patent number: 7989134
    Abstract: To provide a toner manufacturing method including: dissolving or dispersing a toner material into an organic solvent to prepare a toner solution, the toner material containing at least an active hydrogen group-containing compound, polymer reactive with the active hydrogen group-containing compound, binder resin, releasing agent and coloring agent; emulsifying or dispersing the toner solution into an aqueous medium to prepare an emulsified dispersion; reacting the active hydrogen group-containing compound with the polymer reactive with the active hydrogen group-containing compound in the aqueous medium produce an adhesive base material in the form of particle; and removing the organic solvent, wherein time X (hour) from a point where the organic solvent starts to be removed to a point where the concentration of the organic solvent reaches less than 12% by mass and temperature T (° C.) of the emulsified dispersion at the time X satisfy the relationship 5{exp(?0.2X)+1}?T?50X?0.2.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: August 2, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Toshihiko Usami, Masashi Miyakawa
  • Patent number: 7879647
    Abstract: A technique for mounting two semiconductor chips over a wiring substrate including mounting a first chip having first bonding pads over a surface of the wiring substrate having electrodes and stacking the second chip having second bonding pads over the first chip; connecting each of the first bonding pads to an associated one of the electrodes of the wiring substrate via an associated first wire; and connecting each of the second bonding pads to an associated one of the electrodes of the wiring substrate via an associated second wire. The bondings being carried out using a reverse bonding method in which at least one of the first and second wires are first bonded to an associated one of the electrodes of the wiring substrate followed by the bonding thereof to an associated one of the bonding pads of the first or second semiconductor chip.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: February 1, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20100213585
    Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.
    Type: Application
    Filed: January 26, 2010
    Publication date: August 26, 2010
    Inventor: Toshihiko USAMI
  • Publication number: 20100068850
    Abstract: A technique for mounting two semiconductor chips over a wiring substrate including mounting a first chip having first bonding pads over a surface of the wiring substrate having electrodes and stacking the second chip having second bonding pads over the first chip; connecting each of the first bonding pads to an associated one of the electrodes of the wiring substrate via an associated first wire; and connecting each of the second bonding pads to an associated one of the electrodes of the wiring substrate via an associated second wire. The bondings being carried out using a reverse bonding method in which at least one of the first and second wires are first bonded to an associated one of the electrodes of the wiring substrate followed by the bonding thereof to an associated one of the bonding pads of the first or second semiconductor chip.
    Type: Application
    Filed: October 6, 2009
    Publication date: March 18, 2010
    Inventors: Masachika Masuda, Toshihiko Usami