Abstract: A large scale integrated package comprises a substrate having a power supply layer and a signal wiring layer. A plurality of pads for connecting IC terminals are formed on the top surface of the substrate. Additionally, a plurality of spare pads are also provided on the top surface of the substrate. The lower surface of the substrate has a plurality of input/output terminals which can be inserted into connectors. Additionally, the lower surface of the substrate has a plurality of spare terminals. Each of the pads and spare pads are electrically connected through the substrate to a corresponding terminal and spare terminal. A broken connection between a first pad and a first input/output terminal can be repaired by connecting the first pad to a spare pad and the first input/output terminal to the spare input/output terminal corresponding to the spare pad.

Abstract: An integrated circuit package including a multilayer ceramic substrate for mounting a plurality of integrated circuit chips on a first surface thereof. The substrate is provided with a power supply layer, a ground connection layer and circuit patterns. An array of coaxial pins is juxtaposed on the opposite surface of the substrate. Each coaxial pin includes an inner conductor and an outer conductor. The inner conductor of one or more coaxial pins is connected to the power supply layer and the inner conductors of the remaining coaxial pins are connected to the circuit patterns. The outer conductors of all the coaxial pins are connected to the ground connection layer.

Abstract: A multichip package is comprised of a substrate having a grid of input and output pins disposed on an under surface. Power supply and grounding wire layers are embedded in the substrate. An upper surface of the substrate has a plurality of thin wire layers separated by at least one insulating layer. A plurality of via holes in the insulating layer permit conductive interconnection of the wire layers. A plurality of leadless chip carriers on the upper have tape automated bonding leads that are inner lead bonded to the substrate. The chips are directly connected to the substrate and have a plurality of chip carrier terminals on an under surface that connect to the terminal pads. The chip carrier has a cover made of highly heat conductive material that contacts the back side of at least one mounted chip.

Abstract: A multichip package is comprised of a substrate having a grid of input and output pins disposed on an under surface. Power supply and grounding wire layers are embedded in the substrate. An upper surface of the substrate has a plurality of thin wire layers separated by at least one insulating layer. A plurality of via holes in the insulating layer permit conductive interconnection of the wire layers. A plurality of leadless chip carriers on the upper layer have tape automated bonding leads that are inner lead bonded to the substrate. The chips are directly connected to the substrate and have a plurality of chip carrier terminals on an under surface that connect to the terminal pads. The chip carrier has a cover made of highly heat conductive material that contacts the back side of at least one mounted chip.

Abstract: An integrated circuit chip package has a substrate, a plurality of integrated circuit chips, a plurality of heat radiation plates, a heat radiation cover, a heat sink rigidly mounted on the heat radiation cover and a plurality of terminals. The plurality of integrated circuit chips are each provided with a plurality of flexible beam leads on a body thereof and electrically and mechanically connected with the substrate via the beam lead. The heat radiation plates are each composed of a good thermal conductor and rigidly joined with the integrated circuit chips and a one-to-one correspondence by a first adhesive material. A radiation cover is also composed of a good thermo conductor and covers the chip mounting surface of the substrate and is held in contact with the heat radiation plates through a second adhesive material.