Patents by Inventor Toshihiko Yokota
Toshihiko Yokota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8161445Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.Type: GrantFiled: January 17, 2008Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Chaitra M. Bhat, Chandrika Madhwacharya, Atsushi Sugai, Toshihiko Yokota
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Patent number: 8006210Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.Type: GrantFiled: January 15, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Chaitra M. Bhat, Chandrika Madhwacharya, Atsushi Sugai, Toshihiko Yokota
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Patent number: 7930608Abstract: An integrated circuit for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and latches synchronously operated in accordance with operating clock signals distributed via the clock buffers. The circuit comprises a mechanism for performing an At Speed Test to shift data that are initially set for the latches in accordance with the operating clock signals to succeeding latches, respectively. It also has a timing designation circuit for enabling a clock signal pulse when a first output signal pulse is active. In addition, it includes a ring-type oscillator to consume current in the period during which the first output signal is active. The ring-type oscillator includes a delay control input terminal. The oscillation cycle of the ring-type oscillator is selectively adjusted by adjusting an input of the delay control input terminal.Type: GrantFiled: February 22, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventor: Toshihiko Yokota
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Patent number: 7793183Abstract: Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted.Type: GrantFiled: June 8, 2006Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Toshihiko Yokota, Ken Namura, Mitsuru Sugimoto
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Patent number: 7752586Abstract: A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and which is connected to the first flip flop; and a third flip-flop DFF 3 which operates by using the second clock signal CLK 2, and which is connected to the first flip-flop. A test on a path between the first and second flip-flops is carried out in a manner that test data is released and captured on receipt of the clock signal CLK 2 between the second flip-flop DFF 2 and the third flip-flop DFF 3 via the first flip-flop DFF 1, and that the test data is flushed by the first flip-flop DFF 1.Type: GrantFiled: November 20, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventor: Toshihiko Yokota
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Patent number: 7752513Abstract: A method and integrated circuit for LSSD testing. The integrated circuit includes a plurality of clock domains supplied with test clocks from separate clock generation circuits. In each clock domain, a scan latch at a clock domain boundary receiving an input from another clock domain includes a master latch for latching an input in response to a first clock, a slave latch for latching an output from the master latch in response to a second clock, a selector for supplying the master latch with a system input when the mode selection signal is at a second level, and a clock control circuit for turning off the first clock when the mode selection signal transits from the first level to the second level.Type: GrantFiled: February 7, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Ken Namura, Sanae Seike, Toshihiko Yokota
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Publication number: 20090132973Abstract: A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and which is connected to the first flip flop; and a third flip-flop DFF 3 which operates by using the second clock signal CLK 2, and which is connected to the first flip-flop. A test on a path between the first and second flip-flops is carried out in a manner that test data is released and captured on receipt of the clock signal CLK 2 between the second flip-flop DFF 2 and the third flip-flop DFF 3 via the first flip-flop DFF 1, and that the test data is flushed by the first flip-flop DFF 1.Type: ApplicationFiled: November 20, 2007Publication date: May 21, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Toshihiko Yokota
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Publication number: 20090119561Abstract: Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted.Type: ApplicationFiled: June 8, 2006Publication date: May 7, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshihiko Yokota, Ken Namura, Mitsuru Sugimoto
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Publication number: 20080209292Abstract: An integrated circuit and related method for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and a plurality of latches synchronously operated in accordance with operating clock signals distributed via the clock buffers. The circuit comprises a mechanism for performing an At Speed Test to shift data that are initially set for the latches in accordance with the operating clock signals to succeeding latches, respectively. It also has a timing designation circuit for generating a first output signal that is active for a period from a predetermined time, which is after the integrated circuit is powered on and before an operating clock signal for the At Speed Test is generated, to a time when the operating clock signal is generated.Type: ApplicationFiled: February 22, 2008Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Toshihiko Yokota
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Publication number: 20080134110Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.Type: ApplicationFiled: January 17, 2008Publication date: June 5, 2008Inventors: Chaitra M. Bhat, M. Chandrika, Atsushi Sugai, Toshihiko Yokota
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Publication number: 20080115094Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.Type: ApplicationFiled: January 15, 2008Publication date: May 15, 2008Inventors: Chaitra Bhat, M. Chandrika, Atsushi Sugai, Toshihiko Yokota
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Patent number: 7356797Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.Type: GrantFiled: June 14, 2005Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Chaitra M. Bhat, M. Chandrika, Atsushi Sugai, Toshihiko Yokota
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Publication number: 20070198882Abstract: A method and integrated circuit for LSSD testing. The integrated circuit includes a plurality of clock domains supplied with test clocks from separate clock generation circuits. In each clock domain, a scan latch at a clock domain boundary receiving an input from another clock domain includes a master latch for latching an input in response to a first clock, a slave latch for latching an output from the master latch in response to a second clock, a selector for supplying the master latch with a system input when the mode selection signal is at a second level, and a clock control circuit for turning off the first clock when the mode selection signal transits from the first level to the second level.Type: ApplicationFiled: February 7, 2007Publication date: August 23, 2007Inventors: Ken Namura, Sanae Seike, Toshihiko Yokota
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Publication number: 20070124635Abstract: An object of the present invention is to realize an at-speed test on a latch-to-latch path (a cross domain path) between different clock domains. In order to achieve the object, the present invention provides an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and which is connected to the first flip flop; and a third flip-flop DFF 3 which operates by using the second clock signal CLK 2, and which is connected to the first flip-flop. A test on a path between the first and second flip-flops is carried out in a manner that test data is released and captured on receipt of the clock signal CLK 2 between the second flip-flop DFF 2 and the third flip-flop DFF 3 via the first flip-flop DFF 1, and that the test data is flushed by the first flip-flop DFF 1.Type: ApplicationFiled: November 1, 2006Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Toshihiko Yokota
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Publication number: 20060282809Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.Type: ApplicationFiled: June 14, 2005Publication date: December 14, 2006Applicant: International Business Machines CorporationInventors: Chaitra Bhat, M. Chandrika, Atsushi Sugai, Toshihiko Yokota