Abstract: A branching device to send out data received at an arbitrary one of three terminals thereof through the other two terminals. In the device, the terminals are coupled to each other by means of photo-couplers. The head of a data block received by each receiver connected with each terminal is detected, and after such detection of the head, a signal which specifies the length of the data block is generated. Thus, after communication data are received by way of an arbitrary one of the terminals, reception of communication data by way of the other two terminals is inhibited while transmission of the communication data is enabled in response to the signal specifying the data block detected.

Abstract: Among systems configured by connecting a plurality of sequence controllers to one communication line to intercommunicate, many systems has been disclosed which implement fault location and recovery from the faults. In one of these systems, each substation is connected to a circulating communication line via a branch line and switches are respectively disposed on the branch line and on the communication line at both sides of a connecting point of the branch line and the communication line. Further, the communication line can be formed in a loop by a spare line. In another of these systems, an integrated portion of the communication line is formed near the master station, and the communication line is connected to the master station and is configured of one continuous line which goes and backs in sequence between the integrated portion and vicinity of each substation. In that integrated portion, a switch is disposed on each one of two lines, which connect the integrated portion and each substation.

Abstract: A transfer machine is provided with a plurality of machining units disposed in positions to correspond respectively to machining stations which constitute parts of a transfer line. Each of programmable sequence controllers respectively associated with the machining units has a program memory storing a plurality of workpiece-dependent control programs and controls the operation of an associated one of the machining units in accordance with one of the workpiece-dependent control programs designated by a data processor. The data processor is provided with a memory which stores part numbers of the workpieces respectively held on the machining stations and the kinds of machining cycles in which each of the workpieces is scheduled to be machined respectively at the machining stations.

Abstract: A programmable sequence controller using a technique called microprogramming, including a microprogram memory having a plurality of memory sections each storing a set of microinstructions corresponding to the command word of a sequence instruction. The operation code of the sequence instruction is applied to the upper bits of the microprogram memory so as to select one of the memory sections. The remaining bits are determined by a counter and the ON/OFF state of an I/O element so that one of the microinstructions is read out from the selected memory section.

Abstract: A sequence instruction display system for use with a programmable sequence controller for displaying a desired sequence instruction and the on-off state of the input or output element corresponding thereto. A buffer memory is provided for storing input and output instructions along with the corresponding on-off states transmitted from a program memory of the sequence controller on an on-line basis with the scan of the program memory in the sequence controller. A numeric key is provided to designate an output instruction. A comparator, on detecting the coincidence of the designated output instruction with an output instruction transmitted from the sequence controller, outputs a signal so as to prevent the buffer memory from further storing the input and output instructions. A data display device displays at a time one of the input and output instructions along with the on-off state stored in the buffer memory.

Abstract: A sequence instruction display system used with a programmable sequence controller for displaying a desired sequence instruction and the on-off state of the input or output element corresponding thereto. A data processor stores the address data of an input element in an input address register when the on-off state thereof and an input instruction corresponding thereto are displayed. The data processor, when a signal is applied thereto, searches a program storage area for an output instruction having the address data which is stored in the input address register and further searches for an input instruction which concerns the energization of the output element corresponding to the output instruction to thereby enable the operator to find a desired sequence instruction by a simple manipulation.

Abstract: A sequence block display system used with a programmable sequence controller for displaying a sequence block on a screen of a cathode-ray tube display unit in the form of ladder diagram. The sequence block display system is provided with a data processor and a buffer memory which includes first, second and third memories. The first memory is capable of storing the whole of sequence programs stored in the sequence controller and the second memory is capable of storing at least one sequence block. The third memory is adapted to store output instructions, which are used to designate a sequence block, in the same order as each designated sequence block is displayed on the screen and further to read out the output instructions in the reverse order for displaying the sequence blocks which are put out of the screen.

Abstract: A programmable sequence controller with a counting function comprises an addressable latch circuit including at least one flip flop. A counter is connected to the flip flop such that the content of the counter is changed by one each time the flip flop is set. A setting device is provided for manually setting a count-up value of the counter. A comparator generates a count-up value signal when the counting-up of the counter to the count-up value is detected. A data selector is connected to receive the count-up value signal for supplying a logical value indicative of the status of the comparator. A logic operation circuit is responsive to a test command of a first instruction for testing a logical value of one of a plurality of external input devices and the data selector specified by address data in the first instruction and also responsive to an output command in a second instruction for generating an output command signal based upon the result of the test.

Abstract: A programmable sequence controller wherein a logic operation processor controls a program counter so as to successively read out from a sequence memory sequence instructions, which are applied to an input and output selector for selectively designating a plurality of input and output elements as well as to the logic operation rocessor. The logic operation processor is programmed to test the operational states of one or more input elements when receiving test commands and to output an energization or deenergization signal based upon the test result when receiving an output command. An output drive device is provided, which energizes or deenergizes selected one of the output elements in response to the energization or deenergization signal.

Abstract: An output circuit for a programmable sequence controller wherein a load drive element control circuit is responsive to a command signal stored in a memory circuit for controlling a load drive element connected between a load and a first electric supply. Between a power input terminal of the load drive element control circuit and a second electric supply, there is connected in series a switching element, which is switched on in response to a signal applied from a supply voltage detecting circuit only when the voltage level of the second electric supply is not lower than a level sufficient for normal and reliable operation of the load drive element control circuit.

Abstract: In a programmable sequence controller, a memory stores an auxiliary function decoding program comprising command information and address information. A comparator circuit capable of a simultaneous comparison of a plurality of bits is operatively connected to an external numerical control device to receive auxiliary function data therefrom and connected to receive address information of the decoding program for comparing the auxiliary function data with the address information of the decoding program. A logic operation circuit included in the programmable sequence contoller is operatively connected to the comparator circuit to examine the comparison result of the comparator circuit based upon command information of the decoding program, whereby the auxiliary function data is decoded.

Abstract: A programmable sequence controller wherein in accordance with a sequence program read out from a memory, a logic operation circuit tests a logical value supplied from an input converter connected to an external input element and generates an output command signal based upon the result of the test. The output command signal is stored in an output memory which has two storage addresses for each external output element, each storage address corresponding to a particular memory storage element addressed by the sequence program. A gate circuit is connected to these two memory storage elements and inhibits the application of an output command signal from one of the memory storage elements to an output converter when the gate circuit receives a logical value from the input converter. When receiving an output command signal from the other of the two memory storage elements the gate circuit then applies this signal to the output converter.

Abstract: In a programmable sequence controller, a logic operation circuit has first and second AND gates, first and second OR gates and first to fourth flip flops. An input is applied to the two AND gates and the two OR gates. The first and second AND gates receive outputs of the first and second flip flops wich receive outputs of the first and second AND gates and are triggered in response to first and second control commands, respectively. The first and second OR gates receive outputs of the third and fourth flip flops which receive outputs of the first and second OR gates and are triggered in response to third and fourth control commands, respectively. A sequence control is performed in response to the outputs of the first to fourth flip flops.

Abstract: A programmable sequence controller is disclosed which includes a controller memory having at least one read-only memory unit for storing a sequence program comprising a series of instructions each including an operation code and address information. An operation control device is also provided for examining an external input in accordance with an appropriate instruction. An input network permits application of external inputs designated by the address information to the operation control device, and an output network is provided for transmitting a control signal based on the examination result from the operation control device. A program input network including a read-write memory is provided for storing a part of the sequence program, which part is loadable in one read-only memory unit.

Abstract: A sequence controller comprising a logic operation circuit for examining an external input with an examine command in accordance with a program. The logic operation circuit comprises block means for discontinuing a next examination of a logical function of a group of logical functions in response to a preceeding examination result of a logical function to thereby execute a logic operation non-sequentially.