Patents by Inventor Toshihiko Yoshimasu
Toshihiko Yoshimasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11362623Abstract: A voltage-controlled oscillator includes a first transistor, a second transistor, an inductive impedance element, a first variable capacitive impedance element, and a second variable capacitive impedance element. The first transistor has a source coupled to a first power source, a drain coupled to a first node, and a gate coupled to a second node. The second transistor has a source coupled to the first power source, a drain coupled to the second node, and a gate coupled to the first node. The inductive impedance element has a first terminal coupled to the first node and a second terminal coupled to the second node. The first variable capacitive impedance element has a first terminal coupled to the first node and a second terminal coupled to a third node. The second variable capacitive impedance element has a first terminal coupled to the second node and a second terminal coupled to the third node.Type: GrantFiled: October 28, 2020Date of Patent: June 14, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Toshihiko Yoshimasu, Kouki Tanji, Tsuyoshi Sugiura
-
Patent number: 11043919Abstract: A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.Type: GrantFiled: July 26, 2019Date of Patent: June 22, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Toshihiko Yoshimasu, Tadamasa Murakami, Tsuyoshi Sugiura
-
Publication number: 20210167727Abstract: A voltage-controlled oscillator includes a first transistor, a second transistor, an inductive impedance element, a first variable capacitive impedance element, and a second variable capacitive impedance element. The first transistor has a source coupled to a first power source, a drain coupled to a first node, and a gate coupled to a second node. The second transistor has a source coupled to the first power source, a drain coupled to the second node, and a gate coupled to the first node. The inductive impedance element has a first terminal coupled to the first node and a second terminal coupled to the second node. The first variable capacitive impedance element has a first terminal coupled to the first node and a second terminal coupled to a third node. The second variable capacitive impedance element has a first terminal coupled to the second node and a second terminal coupled to the third node.Type: ApplicationFiled: October 28, 2020Publication date: June 3, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Toshihiko Yoshimasu, Kouki Tanji, Tsuyoshi Sugiura
-
Publication number: 20200036340Abstract: A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.Type: ApplicationFiled: July 26, 2019Publication date: January 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Toshihiko Yoshimasu, Tadamasa Murakami, Tsuyoshi Sugiura
-
Publication number: 20150070072Abstract: A harmonic mixer includes first through third field effect transistors. A gate electrode of the first field effect transistor is supplied with a positive-phase signal of a first signal. A gate electrode of the second field effect transistor is supplied with a negative-phase signal of the first signal. A source electrode of the second field effect transistor is short-circuited with a source electrode of the first field effect transistor and is grounded. A source electrode of the third field effect transistor is connected to a terminal at which drain electrodes of the first field effect transistor and the second field effect transistor are short-circuited. A gate electrode of the third field effect transistor is supplied with a second signal. A drain electrode of the third field effect transistor outputs a signal.Type: ApplicationFiled: September 4, 2014Publication date: March 12, 2015Inventors: Toshihiko YOSHIMASU, Takayuki SHIBATA
-
Patent number: 8773224Abstract: A frequency multiplier includes an input circuit, an output circuit, and a resonance circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number ānā multiple of the input signal frequency. The output circuit has a predetermined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to a frequency of the input signal, and such resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit.Type: GrantFiled: November 29, 2011Date of Patent: July 8, 2014Assignees: DENSO CORPORATION, Waseda UniversityInventors: Toshihiko Yoshimasu, Takayuki Shibata
-
Publication number: 20120133400Abstract: A frequency multiplier includes an input circuit, an output circuit, and a resonance circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number ānā multiple of the input signal frequency. The output circuit has a predetermined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to a frequency of the input signal, and such resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit.Type: ApplicationFiled: November 29, 2011Publication date: May 31, 2012Applicants: DENSO CORPORATION, Waseda UniversityInventors: Toshihiko YOSHIMASU, Takayuki SHIBATA
-
Patent number: 5202651Abstract: An image band-stop filter circuit includes a transmission line formed on a substrate of GaAs and a T circuit connected in parallel to the transmission line and having a high pass filter characteristic. The T circuit includes series-connected first and second capacitances connected in parallel to the transmission line and a stub having one end connected to a node between the first and second capacitances and the other end short-circuited. The stub has a line length which becomes inductive in an image signal band to be removed. As a result, the lengths of the transmission line and the stub can be reduced to enable the band-stop filter circuit to be made into a MMIC with ease while achieving an excellent signal transmission characteristic.Type: GrantFiled: December 24, 1991Date of Patent: April 13, 1993Assignee: Sharp Kabushiki KaishaInventor: Toshihiko Yoshimasu
-
Patent number: 5065117Abstract: Disclosed is a microwave circuit suitable made into a monolithic microwave integrated circuit (MMIC). This microwave circuit includes a main line comprising a distributed constant line formed on a major surface of a substrate, and a stub connected in parallel with the main line in which lines the characteristics admittance varies discontinuously. Because of the discontinuous variation of the characteristic admittance of the stub, the phase of the characteristic admittance is changed, so that the stub length can be reduced.Type: GrantFiled: June 5, 1990Date of Patent: November 12, 1991Assignee: Sharp Kabushiki KaishaInventor: Toshihiko Yoshimasu