Abstract: A signal processing apparatus according to the present invention includes: a common pre-processing section for performing signal processing common to a photographed image process and a flicker detection process on an input image signal; a photographed image processing section for performing image signal processing for a displayed image on an image signal from the common pre-processing section; a flicker detection pre-processing section for performing image signal processing for flicker detection on the image signal from the common pre-processing section; and a flicker detecting section for performing flicker detection based on the image signal from the flicker detection pre-processing section.

Abstract: A signal processing apparatus according to the present invention includes: a common pre-processing section for performing signal processing common to a photographed image process and a flicker detection process on an input image signal; a photographed image processing section for performing image signal processing for a displayed image on an image signal from the common pre-processing section; a flicker detection pre-processing section for performing image signal processing for flicker detection on the image signal from the common pre-processing section; and a flicker detecting section for performing flicker detection based on the image signal from the flicker detection pre-processing section.

Abstract: As soon as a write command is input to a nonvolatile memory cell array, an internal charge pump circuit starts pumping. When the pumping is achieved, the writing to the nonvolatile memory cell array is implemented. By keeping the internal charge pump circuit ready for a next write command even after the end of the first write operation, it is possible to cut down the time required for the activation/deactivation of the internal charge pump circuit, which would cause redundancy. When it is determined that no successive write operations are to be performed, the internal charge pump circuit is deactivated. Similar controls are carried out for the other commands which rewrite the contents of the nonvolatile memory cell array.

Abstract: As soon as a write command is input to a nonvolatile memory cell array, an internal charge pump circuit starts pumping. When the pumping is achieved, the writing to the nonvolatile memory cell array is implemented. By keeping the internal charge pump circuit ready for a next write command even after the end of the first write operation, it is possible to cut down the time required for the activation/deactivation of the internal charge pump circuit, which would cause redundancy. When it is determined that no successive write operations are to be performed, the internal charge pump circuit is deactivated. Similar controls are carried out for the other commands which rewrite the contents of the nonvolatile memory cell array.