Abstract: A semiconductor integrated circuit (1) includes first, second and second functional blocks (10, 20 and 30). The first, second and second functional blocks (10, 20 and 30) are coupled together via an inter-block signal line (2). The first functional block (10) includes: a logic circuit (11); a test data output circuit (12), which operates during testing and outputs a predetermined test data pattern; a testing standby circuit (14), which is connected between a selector (13) and an external bidirectional pin and makes the functional block enter a standby state during testing; a tristate buffer (15) that is made to have a high impedance by the testing standby circuit (14); and a decision result output circuit (16), which receives the test data pattern from the second functional block, compares the received test data pattern to an expected value stored therein, and outputs a decision result to a decision result signal line (5).

Abstract: A semiconductor integrated circuit (1) includes first, second and second functional blocks (10, 20 and 30). The first, second and second functional blocks (10, 20 and 30) are coupled together via an inter-block signal line (2). The first functional block (10) includes: a logic circuit (11); a test data output circuit (12), which operates during testing and outputs a predetermined test data pattern; a testing standby circuit (14), which is connected between a selector (13) and an external bidirectional pin and makes the functional block enter a standby state during testing; a tristate buffer (15) that is made to have a high impedance by the testing standby circuit (14); and a decision result output circuit (16), which receives the test data pattern from the second functional block, compares the received test data pattern to an expected value stored therein, and outputs a decision result to a decision result signal line (5).

Abstract: A method of design for testability using scan FF identification of this invention eases generation of test sequences as compared with conventional technique. An FF relation graph is generated from an integrated circuit, FFs having self loops are recognized in the FF relation graph, and all FFs are replaced with scan FFs. FFs not having self loops are sorted in accordance with a predetermined evaluation function indicating the degree of relation with difficulty in generating test sequences. For example, a function indicating the degree of relation with a balanced reconvergence structure is used as the evaluation function. In a sort order thus obtained, with regard to each FF not having self loops, it is determined whether or not the integrated circuit has an n-fold line-up structure in assuming the FF is replaced with a non-scan FF, thereby identifying scan FFs.

Abstract: A method of design for testability using scan FF identification of this invention eases generation of test sequences as compared with conventional technique. An FF relation graph is generated from an integrated circuit, FFs having self loops are recognized in the FF relation graph, and all FFs are replaced with scan FFs. FFs not having self loops are sorted in accordance with a predetermined evaluation function indicating the degree of relation with difficulty in generating test sequences. For example, a function indicating the degree of relation with a balanced reconvergence structure is used as the evaluation function. In a sort order thus obtained, with regard to each FF not having self loops, it is determined whether or not the integrated circuit has an n-fold line-up structure in assuming the FF is replaced with a non-scan FF, thereby identifying scan FFs.