Patents by Inventor Toshihiro Honma

Toshihiro Honma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528041
    Abstract: A method of manufacturing a semiconductor device, including including preparing a semiconductor substrate having first to fourth active regions and field oxides, the third and fourth active regions sandwiching the second active region, and the field oxides isolating the first to fourth active regions; forming a protective film having openings over the second active region and the field oxide which adjoins the second active region, over the semiconductor substrate; forming the first gate insulator on the second active region; removing the protective film; forming second gate insulators thinner than the first gate insulators on the first, third and fourth active regions, respectively; forming gate electrodes on the first gate insulator over the first active region and on the second gate insulator over the second active region; and forming a pair of first doped regions in the first active region and second doped regions in the third and fourth active regions.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: May 5, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Toshihiro Honma
  • Patent number: 7375015
    Abstract: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on the impurity diffused polysilicon film; forming a refractory metal silicide film on the impurity diffusion preventing film; forming a first nitride film on the refractory metal silicide film; patterning the first nitride film, the refractory metal silicide film and the impurity diffusion preventing film on a gate electrode; forming a first spacer constituted by a second nitride film on side surfaces of the first gate electrode; performing anisotropic etching on the impurity diffused polysilicon film with the first and second nitride films as a mask; and performing an oxidation process.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: May 20, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Toshihiro Honma, Masahiro Takahashi
  • Patent number: 7358577
    Abstract: A high voltage field effect transistor according to the present invention has: a p-type low concentration drain region and a low concentration source region formed on both sides of a channel formation region within a n-type region of a semiconductor substrate; a high concentration drain region formed in the low concentration drain region, an impurity concentration of which is higher than that of the low concentration drain region; a gate insulating film that at least covers a surface of the channel formation region; a field oxide film formed on the low concentration drain region so as to be in contact with an end section of the gate insulating film; a gate electrode formed on said gate insulating film and at least a part of said field oxide film so as to cover an entire channel formation region and an end section of said low concentration drain region; and a non-oxide region of the low concentration drain region, on both sides of which there are the gate electrode and the high concentration drain region, and
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 15, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masashi Yamagishi, Toshihiro Honma
  • Publication number: 20080042197
    Abstract: A high voltage field effect transistor according to the present invention has: a p-type low concentration drain region and a low concentration source region formed on both sides of a channel formation region within a n-type region of a semiconductor substrate; a high concentration drain region formed in the low concentration drain region, an impurity concentration of which is higher than that of the low concentration drain region; a gate insulating film that at least covers a surface of the channel formation region; a field oxide film formed on the low concentration drain region so as to be in contact with an end section of the gate insulating film; a gate electrode formed on said gate insulating film and at least a part of said field oxide film so as to cover an entire channel formation region and an end section of said low concentration drain region; and a non-oxide region of the low concentration drain region, on both sides of which there are the gate electrode and the high concentration drain region, and
    Type: Application
    Filed: June 29, 2007
    Publication date: February 21, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Masashi Yamagishi, Toshihiro Honma
  • Publication number: 20060223269
    Abstract: A method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having first to fourth active regions and field oxides, the third and fourth active regions sandwiching the second active region, and the field oxides isolating the first to fourth active regions; forming a protective film having openings over the second active region and the field oxide which adjoins the second active region, over the semiconductor substrate; forming the first gate insulator on the second active region; removing the protective film; forming second gate insulators thinner than the first gate insulators on the first, third and fourth active regions, respectively; forming gate electrodes on the first gate insulator over the first active region and on the second gate insulator over the second active region; and forming a pair of first doped regions in the first active region and second doped regions in the third and fourth active regions.
    Type: Application
    Filed: March 15, 2006
    Publication date: October 5, 2006
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Toshihiro HONMA
  • Publication number: 20060154459
    Abstract: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on the impurity diffused polysilicon film; forming a refractory metal silicide film on the impurity diffusion preventing film; forming a first nitride film on the refractory metal suicide film; patterning the first nitride film, the refractory metal silicide film and the impurity diffusion preventing film on a gate electrode; forming a first spacer constituted by a second nitride film on side surfaces of the first gate electrode; performing anisotropic etching on the impurity diffused polysilicon film with the first and second nitride films as a mask; and performing an oxidation process.
    Type: Application
    Filed: March 6, 2006
    Publication date: July 13, 2006
    Inventors: Toshihiro Honma, Masahiro Takahashi
  • Patent number: 7022594
    Abstract: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on the impurity diffused polysilicon film; forming a silicon-based film on the impurity diffusion preventing film; forming a refractory metal on the silicon-based film; forming a nitride film on the refractory metal silicide film; patterning the impurity diffused polysilicon film, the impurity diffusion preventing film, the silicon-based film, the refractory metal silicide film and the nitride film on a gate electrode; and performing an oxidation process.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: April 4, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Toshihiro Honma, Masahiro Takahashi
  • Publication number: 20040127004
    Abstract: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, comprises the steps of: forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on the impurity diffused polysilicon film; forming a silicon-based film on the impurity diffusion preventing film; forming a refractory metal on the silicon-based film; forming a nitride film on the refractory metal silicide film; patterning the impurity diffused polysilicon film, the impurity diffusion preventing film, the silicon-based film, the refractory metal silicide film and the nitride film on a gate electrode; and performing an oxidation process.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 1, 2004
    Inventors: Toshihiro Honma, Masahiro Takahashi
  • Patent number: 6695597
    Abstract: A scroll fluid machine has a stationary scroll and a revolving scroll, each of which has a spiral scroll wrap spiraling from the center side to the outer side. One of the scrolls has an annular outermost wrap having a radius larger than that at the outer end of the spiral wrap of the other scroll. The annular, outermost wrap is the outermost wall, and the scrolls are assembled so that the wrap of the other scroll is disposed in the inner side of the wrap of the one of the scrolls.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: February 24, 2004
    Assignee: Anest Iwata Corporation
    Inventors: Hideyuki Kimura, Atushi Fukui, Ken Yanagisawa, Toshihiro Honma
  • Publication number: 20010038800
    Abstract: A scroll fluid machine having a stationary scroll and a revolving scroll characterized in that one of the scrolls 12, each scroll having a spiral scroll lap spiraling from the center side to the outer side, has an annular outermost lap 12a having a radius larger than that at the outer end of the spiral lap of the other scroll 11, the annular, outermost lap 12b and 12b′ being the outermost wall, and the scrolls are assembled so that the lap 11a of the other scroll 11 is disposed in the inner side of the lap 12a of the said one of the scrolls.
    Type: Application
    Filed: March 6, 2001
    Publication date: November 8, 2001
    Inventors: Hideyuki Kimura, Atushi Fukui, Ken Yanagisawa, Toshihiro Honma
  • Patent number: 6179590
    Abstract: A scroll mounting member for mounting a drive scroll therein is secured to the left end of a drive shaft coupled to a motor. A rotary bearing is fitted on the outer periphery of the scroll mounting member, and its outer periphery is secured to a scroll housing. The scroll mounting member is disposed for rotation in the scroll housing and is secured to the drive shaft. A bearing retainer for holding the rotary bearing is mounted by bolts via a spring in a mounting portion of the scroll housing. The rotary bearing is adjustable in the thrust direction at the scroll housing. By turning bolts, the rotary bearing is either advanced in the thrust direction via the bearing retainer or retreated, via the bearing retainer and a spring, which, together with the bolts, form an adjusting device. A self-lubricating sleeve seal is axially slidably fitted in an end portion of a driven scroll mounting member.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: January 30, 2001
    Assignee: Anest Iwata Corporation
    Inventors: Toshihiro Honma, Masaki Tsuji, Toru Sato, Shinji Kawazoe
  • Patent number: 5938419
    Abstract: A scroll mounting member for mounting a drive scroll therein is secured to a left end of a drive shaft coupled to a motor. A rotary bearing is fitted on the outer periphery of the scroll mounting member, and its outer periphery is secured to a scroll housing. The scroll mounting member is disposed for rotation in the scroll housing and is secured to the drive shaft. A bearing retainer for holding the rotary bearing is mounted by bolts via a spring in a mounting portion of the scroll housing such that the rotary bearing is adjustable in the thrust direction at the scroll housing. By turning the bolts, the rotary bearing is advanced or retreated in the thrust direction via the bearing retainer or the bearing retainer and a spring which, together with the bolts, provide adjustment. A self-lubricating sleeve seal is axially slidably fitted in an end portion of a rotation of driven scroll mounting member.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: August 17, 1999
    Assignee: Anest Iwata Corporation
    Inventors: Toshihiro Honma, Masaki Tsuji, Toru Sato, Shinji Kawazoe
  • Patent number: 5250828
    Abstract: A semiconductor memory device has a stacked capacitor cell structure which is composed of two MIS transistors and one capacitor. One MIS transistor is formed between a charge accumulation electrode (storage node), and a substrate and an opposite conductive type diffusion layer region. This arrangement can reduce the charge flowing out of and into the substrate and the opposite conductive type diffusion layer region, thus improving the charge holding time.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: October 5, 1993
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshihiro Honma
  • Patent number: 4593267
    Abstract: A digital data code conversion circuit for a variable-word-length data code includes a data code conversion portion and a preparation circuit. In the preparation circuit, a variable-word-length data code having a word length greater than a number n is divided into a plurality of variable-word-length data codes having a word length less than or equal to the number n. The divided variable-word-length data codes are converted into fixed-word-length data codes having a word length n in the data code conversion portion.
    Type: Grant
    Filed: June 30, 1983
    Date of Patent: June 3, 1986
    Assignees: Nippon Telegraph & Telephone Public Corporation, Fujitsu Limited
    Inventors: Hideo Kuroda, Naoki Mukawa, Kiichi Matsuda, Toshihiro Honma, Hiroshi Fukuda