Patents by Inventor Toshihiro Iizuka

Toshihiro Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SINTERED MATERIAL, SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SINTERED MATERIAL
    Publication number: 20230174429
    Abstract: Provided are a sintered material having high corrosion resistance, a method of manufacturing the sintered material, a member for a semiconductor manufacturing apparatus, a method of manufacturing a member for a semiconductor manufacturing apparatus, a semiconductor manufacturing apparatus, and a method of manufacturing a semiconductor manufacturing apparatus. The sintered material according to an embodiment includes 50 mass% or more of yttrium oxyfluoride, has a relative density of 97.0% or more, and has a Vickers hardness of 5.0 GPa or more. The method of manufacturing a sintered material according to an embodiment includes forming a molded body including yttrium oxyfluoride powder having a particle size of 0.3 µm or less, and sintering the molded body under an atmospheric pressure at a temperature of 800° C. or less.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 8, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhwan KIM, Takafumi Noguchi, Toshihiro IIzuka, Younseon Wang, Kenichi Nagayama
  • Member, method of manufacturing the same, apparatus for manufacturing the same, and semiconductor manufacturing apparatus
    Patent number: 11424140
    Abstract: A member includes a base material structure and a surface layer on the base material structure. The surface layer includes a particle that includes Y—O—F. The base material structure includes interface layers in contact with the surface layer. The interface layers of the base material structure include fluorine.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhwan Kim, Toshihiro Iizuka, Kenichi Nagayama, Takafumi Noguchi
  • APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20220223384
    Abstract: An apparatus for manufacturing a semiconductor device may include a vacuum chamber, an electrostatic chuck (ESC), a cooler, an RF plate, a casing, a base plate and a gas supplier. The ESC may be arranged in the vacuum chamber. The cooler may be configured to cool the ESC. The RF plate may be arranged under the cooler. The casing may be configured to support the cooler. The base plate may be opposite to the RF plate to form an inner space together with the casing. The gas supplier may supply a gas having a low dew point to the inner space. Thus, a generation of the dew condensation at the very low temperature may be prevented so that a damage caused by a short, which may be generated by the dew condensation, may also be prevented.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 14, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Naoyuki TAKADA, Noriaki IMAI, Takafumi NOGUCHI, Toshihiro IIZUKA, Yoshiaki MORIYA
  • SINTERED BODY, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR FABRICATING DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR FABRICATING DEVICE
    Publication number: 20220162083
    Abstract: A sintered body, a method of fabricating the sintered body, a semiconductor fabricating device, and a method of fabricating the semiconductor fabricating device, the sintered body including 50 mass % or more of Y5O4F7, wherein the sintered body has a relative density of 97.0% or more and a Vickers hardness of 2.4 GPa or more.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 26, 2022
    Inventors: Chang Hwan KIM, Takafumi NOGUCHI, Toshihiro IIZUKA, Kenichi NAGAYAMA
  • MEMBER, METHOD OF MANUFACTURING THE SAME, APPARATUS FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR MANUFACTURING APPARATUS
    Publication number: 20210111044
    Abstract: A member includes a base material structure and a surface layer on the base material structure. The surface layer includes a particle that includes Y—O—F. The base material structure includes interface layers in contact with the surface layer. The interface layers of the base material structure include fluorine.
    Type: Application
    Filed: September 28, 2020
    Publication date: April 15, 2021
    Inventors: CHANGHWAN KIM, Toshihiro Iizuka, Kenichi Nagayawa, Takafumi Noguchi
  • Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same
    Patent number: 10797061
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Toshihiro Iizuka, Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan
  • Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same
    Patent number: 10797060
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan, Akio Nishida, Toshihiro Iizuka
  • Semiconductor device including a plurality of nitride semiconductor layers
    Patent number: 10658469
    Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro Iizuka, Shin Koyama, Yoshitake Kato
  • METHODS AND APPARATUS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY
    Publication number: 20190034125
    Abstract: A method is provided that includes forming a bit line above the substrate, the bit line disposed in a first direction, after forming the bit line, forming a word line above a substrate, the word line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.
    Type: Application
    Filed: July 25, 2017
    Publication date: January 31, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Mitsuteru Mushiga, Toshihiro Iizuka, Akio Nishida, Tuan Pham
  • Methods and apparatus for three-dimensional nonvolatile memory
    Patent number: 10115899
    Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line by selectively forming a conductive oxide material layer adjacent the word line, and forming a semiconductor material layer adjacent the bit line, and forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 30, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Yusuke Yoshida, Tomohiro Uno, Tomoyuki Obu, Takeki Ninomiya, Toshihiro Iizuka
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    Publication number: 20170047409
    Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.
    Type: Application
    Filed: May 1, 2014
    Publication date: February 16, 2017
    Inventors: Toshihiro IIZUKA, Shin KOYAMA, Yoshitake KATO
  • Silicided bit line for reversible-resistivity memory
    Patent number: 9443910
    Abstract: A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the bit lines. The reversible resistivity material may be a metal oxide. The metal that is used to form the silicide may serve as an oxygen scavenger to draw oxygen away from the silicon, thus preventing formation of silicon oxide between the reversible resistivity material and the bit line. The metal silicide may also help prevent formation of a depletion layer in silicon in the bit line.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Kan Fujiwara, Takuya Futase, Toshihiro Iizuka, Shin Kikuchi, Yoichiro Tanaka, Akio Nishida, Christopher J Petti
  • METHOD FOR FABRICATING A METAL-INSULATOR-METAL (MIM) CAPACITOR HAVING CAPACITOR DIELECTRIC LAYER FORMED BY ATOMIC LAYER DEPOSITION (ALD)
    Publication number: 20140327064
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Toshihiro IIZUKA, Tomoe YAMAMOTO, Mami TODA, Shintaro YAMAMICHI
  • Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)
    Patent number: 8815678
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 26, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Method of manufacturing a semiconductor device
    Patent number: 8440521
    Abstract: A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Naomi Fukumaki, Eiji Hasegawa, Toshihiro Iizuka, Ichiro Yamamoto
  • SEMICONDUCTOR DEVICE HAVING A THIN FILM CAPACITOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20120261735
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO.sub.2, HfO.sub.2, (Zr.sub.x, Hf.sub.1?x)O.sub.2 (0<x<1), (Zr.sub.y, Ti.sub.1?y)O.sub.2 (0<y<1), (Hf.sub.z, Ti.sub.1?z)O.sub.2 (0<z<1), (Zr.sub.k, Ti.sub.l, Hf.sub.m)O.sub.2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro IIZUKA, Tomoe YAMAMOTO, Mami TODA, Shintaro YAMAMICHI
  • Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure
    Patent number: 8212299
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1?x)O2(0<x<1), (Zry, Ti1?y)O2(0<y<1), (Hfz, Ti1?z)O2(0<z<1), (Zrk,Til, Hfm)O2(0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Semiconductor device with complementary transistors that include hafnium-containing gate insulators and metal gate electrodes
    Patent number: 8188547
    Abstract: A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 29, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenzo Manabe, Toshihiro Iizuka, Daisuke Ikeno
  • Metal-insulator-metal (MIM) capacitor having capacitor dielectric material selected from a group consisting of ZRO2, HFO2, (ZRX, HF1-X)O2 (0
    Patent number: 8169013
    Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one o
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Method of manufacturing a semiconductor device
    Publication number: 20120028455
    Abstract: A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.
    Type: Application
    Filed: June 27, 2011
    Publication date: February 2, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Naomi FUKUMAKI, Eiji HASEGAWA, Toshihiro IIZUKA, Ichiro YAMAMOTO