Patents by Inventor Toshihiro Iwasaki
Toshihiro Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160079204Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thicknType: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Inventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
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Publication number: 20160027723Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.Type: ApplicationFiled: September 30, 2015Publication date: January 28, 2016Inventors: Shinji BABA, Toshihiro IWASAKI, Masaki Watanabe
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Publication number: 20160027715Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.Type: ApplicationFiled: July 20, 2015Publication date: January 28, 2016Inventors: Shinji WATANABE, Sumikazu HOSOYAMADA, Shingo NAKAMURA, Hiroshi DEMACHI, Takeshi MIYAKOSHI, Tomoshige CHIKAI, Kiminori ISHIDO, Hiroaki MATSUBARA, Takashi NAKAMURA, Hirokazu HONDA, Yoshikazu KUMAGAYA, Shotaro SAKUMOTO, Toshihiro IWASAKI, Michiaki TAMAKAWA
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Publication number: 20150371934Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.Type: ApplicationFiled: June 19, 2015Publication date: December 24, 2015Inventors: Hirokazu HONDA, Shinji WATANABE, Toshihiro IWASAKI, Kiminori ISHIDO, Koichiro NIWA, Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Shotaro SAKUMOTO, Hiroaki MATSUBARA
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Patent number: 9171791Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.Type: GrantFiled: April 9, 2014Date of Patent: October 27, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinji Baba, Toshihiro Iwasaki, Masaki Watanabe
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Patent number: 9171814Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: GrantFiled: March 11, 2015Date of Patent: October 27, 2015Assignee: Renesas Electronics CorporationInventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Publication number: 20150187720Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Patent number: 8994175Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: GrantFiled: December 24, 2013Date of Patent: March 31, 2015Assignee: Renesas Electronics CorporationInventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Publication number: 20140284789Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: ApplicationFiled: December 24, 2013Publication date: September 25, 2014Applicant: Renesas Electronics CorporationInventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Publication number: 20140217582Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shinji BABA, Toshihiro IWASAKI, Masaki WATANABE
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Patent number: 8729709Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.Type: GrantFiled: January 12, 2011Date of Patent: May 20, 2014Assignee: Renesas Electronics CorporationInventors: Shinji Baba, Toshihiro Iwasaki, Masaki Watanabe
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Publication number: 20120098126Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.Type: ApplicationFiled: October 14, 2011Publication date: April 26, 2012Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA
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Publication number: 20110169170Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.Type: ApplicationFiled: January 12, 2011Publication date: July 14, 2011Inventors: Shinji BABA, Toshihiro Iwasaki, Masaki Watanabe
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Patent number: 7951699Abstract: A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so that the solder paste is ref lowed, a third step of bonding the metal posts of the mother chip and metal posts of a daughter chip to each other in a thermocompression bonding manner by means of the solder film after the second step, and a fourth step of flip-chip-connecting the mother chip on a circuit substrate by using the solder balls. In the second step, the mother chip is heated in a nitrogen atmosphere in which the oxygen concentration is 500 ppm or less.Type: GrantFiled: December 12, 2006Date of Patent: May 31, 2011Assignee: Renesas Electronics CorporationInventors: Toshihiro Iwasaki, Shiori Idaka, Yasumichi Hatanaka
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Patent number: 7745258Abstract: A manufacturing method of the semiconductor device including a step of forming solder balls on the circuit face of a mother chip, a step of making flip chip bonding of the daughter chip after the step of forming solder balls on the circuit face of the mother chip, and a step of making flip chip bonding of the mother chip on a circuit board using the solder balls.Type: GrantFiled: July 14, 2008Date of Patent: June 29, 2010Assignee: Renesas Technology Corp.Inventors: Toshihiro Iwasaki, Michitaka Kimura, Kozo Harada
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Publication number: 20080274590Abstract: A manufacturing method of the semiconductor device including a step of forming solder balls on the circuit face of a mother chip, a step of making flip chip bonding of the daughter chip after the step of forming solder balls on the circuit face of the mother chip, and a step of making flip chip bonding of the mother chip on a circuit board using the solder balls.Type: ApplicationFiled: July 14, 2008Publication date: November 6, 2008Applicant: Renesas Technology Corp.Inventors: Toshihiro Iwasaki, Michitaka Kimura, Kozo Harada
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Patent number: 7443036Abstract: The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter chip after the step forming solder balls on the circuit face of the mother chip, and a step making flip chip bonding of the mother chip on a circuit board using the solder balls.Type: GrantFiled: October 4, 2005Date of Patent: October 28, 2008Assignee: Renesas Technology Corp.Inventors: Toshihiro Iwasaki, Michitaka Kimura, Kozo Harada
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Publication number: 20070141750Abstract: A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so that the solder paste is ref lowed, a third step of bonding the metal posts of the mother chip and metal posts of a daughter chip to each other in a thermocompression bonding manner by means of the solder film after the second step, and a fourth step of flip-chip-connecting the mother chip on a circuit substrate by using the solder balls. In the second step, the mother chip is heated in a nitrogen atmosphere in which the oxygen concentration is 500 ppm or less.Type: ApplicationFiled: December 12, 2006Publication date: June 21, 2007Inventors: Toshihiro Iwasaki, Shiori Idaka, Yasumichi Hatanaka
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Publication number: 20060134832Abstract: The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter chip after the step forming solder balls on the circuit face of the mother chip, and a step making flip chip bonding of the mother chip on a circuit board using the solder balls.Type: ApplicationFiled: October 4, 2005Publication date: June 22, 2006Applicant: Renesas Technology Corp.Inventors: Toshihiro Iwasaki, Michitaka Kimura, Kozo Harada
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Publication number: 20050046036Abstract: A semiconductor device containing a semiconductor chip is provided with a coupling portion allowing coupling to a neighboring semiconductor device. The coupling portions couple the plurality of semiconductor devices to form a substrate, and a semiconductor package is arranged on the substrate via an electrode arranged on a surface of the substrate. This structure can improve a packaging density.Type: ApplicationFiled: August 25, 2004Publication date: March 3, 2005Inventor: Toshihiro Iwasaki