Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

Abstract: A method and a program capable of controlling an error rate of device-specific information are provided.

Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.

Abstract: A method and a program capable of controlling an error rate of device-specific information are provided.

Abstract: This invention provides an electronic circuit component authenticity determination method capable of determining whether an electronic circuit component is a component manufactured by an authorized manufacturer. The electronic circuit component is operated under a predetermined condition at the time of manufacturing or initialization of the electronic circuit component. The waveform of power consumption or an electromagnetic wave at the time of the operation is measured and stored as first waveform data. An authenticity determination target electronic circuit component is operated under the predetermined condition. The waveform of power consumption or an electromagnetic wave is measured and temporarily stored as second waveform data. The stored first waveform data is compared with the second waveform data. It is determined that the electronic circuit component is a genuine when the waveform data match.

Abstract: A physical unclonable function (PUF) device, and a PUF reader which extracts PUF parameters required to calculate a response output from a challenge input by analyzing an operation of the PUF device. Operation parameters characterizing an operation state are obtained by observing a power waveform, an electromagnetic waveform, or a processing time of the PUF device at that time. Authentication of the PUF device is based on the extracted parameters. The PUF reader executes authenticity determination as to whether or not the PUF device is a valid PUF device by monitoring an operation of the PUF device during response generation based on the operation parameters.

Abstract: Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized.

Abstract: An image display apparatus for displaying image signals of a form of packets incorporating display position information includes a combination of unit display devices so as to acquire translational objectivity. Each of the unit display devices including a receiving part for receiving image signals, a processing part for dividing input image signals into those falling inside and those falling outside a range for display or those subject to or those not subject to display based on the display position information and serving to process display positions of the image signals falling outside the range for display or not subject to display, an output part for outputting the processed image signals along an axis of translational objectivity to a subsequent unit display device, and a display part for displaying the images falling in the range for display, the image display apparatus displaying the image signals as a whole, with the image signals processed sequentially with the unit display devices.

Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

Abstract: An image display apparatus for displaying image signals of a form of packets incorporating display position information includes a combination of unit display devices so as to acquire translational objectivity. Each of the unit display devices including a receiving part for receiving image signals, a processing part for dividing input image signals into those falling inside and those falling outside a range for display or those subject to or those not subject to display based on the display position information and serving to process display positions of the image signals falling outside the range for display or not subject to display, an output part for outputting the processed image signals along an axis of translational objectivity to a subsequent unit display device, and a display part for displaying the images falling in the range for display, the image display apparatus displaying the image signals as a whole, with the image signals processed sequentially with the unit display devices.

Abstract: A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2n bits. For example, when m2n bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2n bits, a CRC circuit that processes every m2(n?1) bits, . . . , and a CRC circuit that processes every m20 bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2n bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

Abstract: Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized.