Patents by Inventor Toshihiro Kitano

Toshihiro Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Voltage generating circuit causing no threshold voltage loss by FET in output voltage
    Patent number: 5357416
    Abstract: An improved substrate bias voltage generating circuit provided in a semiconductor device such as a DRAM is disclosed. In a conducting period of an NMOS transistor (8) provided in a last stage, a higher enough voltage than a source voltage (i.e. an output voltage V.sub.BB) can be applied to a gate of the transistor (8). Loss for a threshold voltage of the transistor (8) does not occur in the output voltage V.sub.BB ; the substrate bias voltage V.sub.BB of a level -Vcc can be generated.
    Type: Grant
    Filed: June 4, 1993
    Date of Patent: October 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Kitano, Takeshi Kajimoto