Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor integrated circuit includes a first functional circuit block; a second functional circuit block; a relay circuit block; a first protection circuit block; and a second protection circuit block. The first protection circuit block includes an ESD protection circuit connected between either one of a first high-voltage power supply line and a first low-voltage power supply line, and either one of a third high-voltage power supply line and a third low-voltage power supply line. The second protection circuit block includes an ESD protection circuit connected between either one of a second high-voltage power supply line and a second low-voltage power supply line, and either one of the third high-voltage power supply line and the third low-voltage power supply line.

Abstract: A semiconductor device includes a protected circuit and an electrostatic-discharge protection circuit. The electrostatic-discharge protection circuit includes a first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other in a semiconductor substrate, a first impurity diffusion layer of the first conductivity type and a third impurity diffusion layer of the second conductivity type formed apart from each other in the first well, and a second impurity diffusion layer of the second conductivity type and a fourth impurity diffusion layer of the first conductivity type formed apart from each other in the second well. The second and the third impurity diffusion layers are formed adjacent to each other interposing an element isolation region provided across a border between the first and the second wells.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor integrated circuit device includes: a protected circuit protected against electro-static discharge applied from outside the device; an SCR protection circuit having an anode terminal connected to a power line, a cathode terminal connected to a ground line and a trigger terminal; and a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line.

Abstract: A semiconductor integrated circuit device includes: a protected circuit protected against electro-static discharge applied from outside the device; an SCR protection circuit having an anode terminal connected to a power line, a cathode terminal connected to a ground line and a trigger terminal; and a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line.