Abstract: An attachment structure for an exhaust gas sensor, wherein an exhaust gas sensor is attached to a downstream connection pipe part of an exhaust pipe so as to be disposed, in a side view of a motorcycle, in a spatial region between a footrest and a brake pedal provided to the motorcycle.

Abstract: A saddle riding vehicle includes a unit swing engine swingably supported on a body frame through a link member, and an exhaust device provided with an exhaust pipe and a catalyst device. The link member is disposed on an upper side of a crankcase. Part of the catalyst device is disposed below a cylinder section and is located in a region between an imaginary line that connects a link member coupling section coupling the link member to the body frame and a front end of the crankcase and an imaginary line that connects an exhaust pipe connection section of the unit swing engine connected with an end of the exhaust pipe and the link member coupling section, in side view. An exhaust device coupling section that couples the crankcase and the exhaust device is provided.

Abstract: A saddle riding vehicle includes a unit swing engine swingably supported on a body frame through a link member, and an exhaust device provided with an exhaust pipe and a catalyst device. The link member is disposed on an upper side of a crankcase. Part of the catalyst device is disposed below a cylinder section and is located in a region between an imaginary line that connects a link member coupling section coupling the link member to the body frame and a front end of the crankcase and an imaginary line that connects an exhaust pipe connection section of the unit swing engine connected with an end of the exhaust pipe and the link member coupling section, in side view. An exhaust device coupling section that couples the crankcase and the exhaust device is provided.

Abstract: An attachment structure for an exhaust gas sensor (74), wherein an exhaust gas sensor (74) is attached to a downstream connection pipe part (68c) of an exhaust pipe (66) so as to be disposed, in a side view of a motorcycle (10), in a spatial region between a footrest (78) and a brake pedal (76) provided to the motorcycle (10).

Abstract: An electronic device using quantum dots, which comprises a ferromagnetic micro magnet and performs individual ESR control on each multi-quantum bit in a power saving way. The electronic device comprising the ferromagnetic micro magnet (10) disposed in the vicinity of the quantum dots (8, 9) of a plurality of aligned semiconductor quantum dots, wherein a strong magnetic field is applied so as to induce electron spin resonance (ESR), and the layout of the ferromagnetic micro magnet (10) is changed, thereby controlling the resonance frequency of the quantum dots (8, 9). Under the condition where the resonance frequency of each quantum dot (8, 9) is controlled, swapping of the electron spins in the quantum dots (8, 9) is performed, thereby creating a quantum bit (QUBIT) required for quantum calculation.

Abstract: An electronic device using quantum dots, which comprises a ferromagnetic micro magnet and performs individual ESR control on each multi-quantum bit in a power saving way. The electronic device comprising the ferromagnetic micro magnet (10) disposed in the vicinity of the quantum dots (8, 9) of a plurality of aligned semiconductor quantum dots, wherein a strong magnetic field is applied so as to induce electron spin resonance (ESR), and the layout of the ferromagnetic micro magnet (10) is changed, thereby controlling the resonance frequency of the quantum dots (8, 9). Under the condition where the resonance frequency of each quantum dot (8, 9) is controlled, swapping of the electron spins in the quantum dots (8, 9) is performed, thereby creating a quantum bit (QUBIT) required for quantum calculation.

Abstract: The invention provides a power control device for a computing unit, which is optimal for saving power. When MPEG data is supplied, a CPU starts decoding the MPEG data. The MPEG data is decoded by independently decoding video data and music data. When decoding the MPEG data, in each operation unit included in the MPEG data, the clock frequency of the CPU can be adjusted so as to reduce the power consumption of the CPU on the basis of the data length of the operation unit for a period during which the CPU performs an operation on the data in the operation unit.

Abstract: The invention provides a data transfer device for multidimensional memory capable of performing an efficient SIMD operation and suitable for transferring data between a multidimensional memory and a one-dimensional memory. A DMAC reads data of a rectangular area in a logical two-dimensional space of a two-dimensional data access memory, and writes the read data on a one-dimensional data access memory. Further, it reads data from the one-dimensional data access memory, and writes the read data on the two-dimensional data access memory, such that the data are arranged in the rectangular area in the logical two-dimensional space of the two-dimensional data access memory.

Abstract: To provide a method of using a memory that can contribute to an efficient SIMD operation. The method of using the memory includes the steps of: supposing a predefined two dimensional memory space consisting of predefined virtual minimum two dimensional memory spaces 1 arranged in longitudinal and transverse directions; and preassigning each address of the virtual minimum two dimensional memory space 1 to an address in each of n physical memories determined in relation with the virtual minimum two dimensional memory space.

Abstract: To provide a data transfer device for multidimensional memory capable of performing an efficient SIMD operation and suitable for transferring data between a multidimensional memory and a one-dimensional memory. A DMAC 43 reads data of a rectangular area in a logical two-dimensional space of a two-dimensional data access memory 10, and writes the read data on a one-dimensional data access memory 41. Further, it reads data from the one-dimensional data access memory 41, and writes the read data on the two-dimensional data access memory 10 such that the data are arranged in the rectangular area in the logical two-dimensional space of the two-dimensional data access memory 10.

Abstract: To provide a power control device for a computing unit, which is optimal for saving power. When MPEG data is supplied, a CPU 30 starts decoding the MPEG data. The MPEG data is decoded by independently decoding video data 304 and music data 306. When decoding the MPEG data, in each operation unit included in the MPEG data, the clock frequency of the CPU 30 is adjusted so as to reduce the power consumption of the CPU 30 on the basis of the data length Lv or La of the operation unit for a period during which the CPU 30 performs an operation on the data in the operation unit.

Abstract: To provide a method of using a memory that can contribute to an efficient SIMD operation. The method of using the memory includes the steps of: supposing a predefined two dimensional memory space consisting of predefined virtual minimum two dimensional memory spaces 1 arranged in longitudinal and transverse directions; and preassigning each address of the virtual minimum two dimensional memory space 1 to an address in each of n physical memories determined in relation with the virtual minimum two dimensional memory space.

Abstract: An error rate measuring apparatus includes a demodulator, and data from the demodulator is applied to a decoding circuit in which an error bit number is evaluated for each of a BIC portion and a packet portion. In the BIC portion, if a synchronization is settled, the error bit number is evaluated by comparing received BICs and a predetermined BIC pattern, and if the synchronization is not settled, the error bit number is determined as eight (8) bits. In the packet portion, if a frame synchronization is settled and decoding is successful, the error bit number is calculated by comparing data before decoding and data after decoding with each other. If the frame synchronization is settled but the decoding is unsuccessful, a presumed error bit number is set according to the number of packets being decoded successfully in a first time horizontal direction, and if the frame synchronization is not settled, a predetermined error bit number is set.