Abstract: A storage system having a plurality of storages. The each of the storages include a memory and a processor coupled to the memory. The processor executes a process including transmitting an update request for data which is commonly stored in the plurality of storages according to a predetermined transmission order indicating a path to transfer the update request. The process includes updating data when receiving an update request from another storage. The process includes changing the predetermined transmission order to a transmission order in which one or more storages included in the path are excluded according to the number of times the update request for the data is received.

Abstract: An internode put requesting unit detects a time-out with respect to a put request issued to the next node in the order of a multiplexing chain and notifies a put/get executing unit of the time-out. The put/get executing unit sends an error to the previous node in the order of the multiplexing chain or a client and instructs a put-failed-data synchronizing unit to synchronize data failed to be put, and the put-failed-data synchronizing unit performs a synchronization process. A primary makes other put requests wait until completion of the synchronization process. Furthermore, when having received the error, the client issues a get request to the tail end of the multiplexing chain.

Abstract: A storage device is one of a plurality of storage devices storing replicas of data. The storage device includes a memory and a processor coupled to the memory. The processor executes a process includes transmitting an update request to at least one destination storage device through a plurality of paths when the storage device is requested to update the data by a client. The process includes notifying the client that the updating of the data has been completed when having received a response through one of the paths, the response being issued by the destination storage device serving as the terminal point of the path when the destination storage device receives the update request through all the paths having the destination storage device as the terminal point.

Abstract: A computer-readable recording medium stores a program that causes a computer to execute a writing control process that includes receiving a writing request to write a first data to a first storage apparatus; determining a second data from among a series of data and based on a writing sequence of the series of data written to the computer and a count of storage areas at a second storage apparatus that sequentially selects from among the storage areas when data is received, a storage area to be over written by the received data, where the second data is written to the first storage apparatus and is identical to data that is stored in the storage area to be selected next at the second storage apparatus; and transmitting copy data of the first data to the second storage apparatus, when the second data has been written to the first storage apparatus.

Abstract: The disclosed method includes obtaining a result concerning a busy rate and the number of accesses per unit time for a storage device including first and second storage areas; determining, from the result, whether an event that a first indicator value for the busy rate is reset occurs; when the event occurred, notifying a controller that makes the number of accesses for the second storage area not greater than the notified number of accesses of the first number of accesses less than the second number of accesses, which was notified immediately before; obtaining another result; updating the first indicator value based on another result; calculating the third number of accesses so that a sum of busy rates corresponding to the third number of accesses and corresponding to the designated number of accesses becomes equal to the updated first indicator value; and notifying the controller of the third number of accesses.

Abstract: A data management apparatus sends specific data and key information corresponding to the specific data to another apparatus, when executing a process to change a storage destination of the specific data in which the hash value obtained by applying a predetermined hash function to corresponding key information belongs to a certain range, from the data management apparatus to the other apparatus, and sends the identification information of the other apparatus stored in correspondence with the certain range to a request source of an operation request, when the operation request with respect to data corresponding to key information is received after the process.

Abstract: Upon receipt of a first key and first data, a control unit exercises control to store second data indicating a second key in association with the first key in a first node and to store the first data in association with the second key in a second node. Upon receipt of an access request that specifies the first key, the control unit detects that data stored in association with the first key is the second data, and accesses the first data stored in the second node on the basis of the second key indicated by the second data.

Abstract: A control unit shifts a boundary between a range of hash values allocated to a first node and a range of hash values allocated to a second node from a first hash value to a second hash value to thereby expand the range of hash values allocated to the first node. The control unit moves data which is part of data stored in the second node and in which hash values calculated from associated keys belong to a range between the first hash value and the second hash value, from the second node to the first node.

Abstract: An information processing apparatus includes a first storage unit and a processor. The first storage unit includes a first storage area. The processor receives a first request to write first data into the first storage area. The processor requests an external apparatus to write the first data into a second storage area in a second storage unit included in the external apparatus. The processor determines whether a first response has been received from the external apparatus. The first response indicates that the first data has been written into the second storage area. The processor writes the first data into the first storage area when the first response has been received. The processor requests, without writing the first data into the first storage area, the external apparatus to write second data stored in the first storage area into the second storage area when the first response has not been received.

Abstract: An information processing system includes a first processor to store data segments in a first memory, to send the data segments to be stored in the first memory to a second processor, and to read the data segments from the first memory so as to store the data segments in a second memory; and the second processor to store the data segments to be stored sent from the first processor in a third memory, wherein when the first processor notifies the second processor about data that is permitted to be removed, the first processor sends ID information to the second processor that renders a particular data segment that was last stored in the second memory identifiable, and the second processor removes from the third memory the particular data segment and an older data segment stored previous to the particular data segment from the data segments stored in the third memory.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: An instruction processing method includes generating a translated code block for an instruction, among instructions included in a target program to be executed and for which a number of executions through sequential interpretation is greater than or equal to a threshold, and storing the generated translated code block in a first storage unit and removing part or all of the translated code block from the first storage unit at a given timing, wherein the generating reduces the threshold with respect to the number of executions over a given period of time after the part or all of the translated code block is removed.

Abstract: A file server has a conversion table that stores therein, in a corresponding manner, logical addresses specified by a higher-level layer and physical addresses specified by a disk driver that are address information indicative of a storage area in a disk device. The file server accesses the disk device with a storage area indicated by a physical address as an access destination and counts up the number of access requests to each storage area in a given period of time for each of the logical addresses. The file server then updates the conversion table such that the physical addresses are lined up in a descending order of the logical addresses of a higher number of the access requests counted. Thereafter, the file server changes storage areas of data stored in the storage device based on the conversion table updated.

Abstract: A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration information and execute a prescribed process. Memory units store configuration information for the processing elements. A memory switching unit switches the plurality of memory units to store therein the configuration information on the stages of a pipeline process to be performed by the processing elements. A configuration information output unit switches the memory units to output therefrom the configuration information to the plurality of processing elements.

Abstract: A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration information and execute a prescribed process. Memory units store configuration information for the processing elements. A memory switching unit switches the plurality of memory units to store therein the configuration information on the stages of a pipeline process to be performed by the processing elements. A configuration information output unit switches the memory units to output therefrom the configuration information to the plurality of processing elements.

Abstract: A migration program which reduces a service suspension time, ensures access transparency and position transparency, and enables normal operation without degrading the performance. When processing is migrated from a source computer, an operating reception block receives an operating system program through a network. An execution information reception block receives execution information needed to resume a process of the source computer, through the network from the source computer. An address reception block receives a floating MAC address assigned to the source computer in addition to the inherent MAC address, from the source computer. A processing block executes processing to restore the state of the source computer in accordance with the received operating system program and execution information, and performs subsequent communication by using the received floating MAC address of the source computer.

Abstract: A heap is a memory resource managed in units of cells and it is used in units of cells by the execution of an application program. A full garbage collection unit collects free cells based on the check result of the state of use of cells. A partial garbage collection unit collects free cells from cells that are used after the check of the state of use of cells recently made by the full garbage collection unit, based on the check result of the state of use of cells. A full/partial control unit improves the process efficiency of parallel type garbage collection by making either the full garbage collection unit or the partial garbage collection unit perform a subsequent collection of free cells based on the state of collections made in the past.

Abstract: To an existing instruction set, newly added are a condition code conversion instruction for converting a first condition code (N, Z, OV, C) to a second condition code (V, S) based on a reference condition code COND, a second conditional instruction having a reference flag SF, and an instruction of operation between two selected second condition codes. A VLIW processor comprises a second condition code register file 163, a condition code conversion circuit 12A, and a logic operation circuit 12E for performing a non-Boolean logic operation between two selected second condition codes.

Abstract: A heap is a memory resource managed in units of cells and it is used in units of cells by the execution of an application program. A full garbage collection unit collects free cells based on the check result of the state of use of cells. A partial garbage collection unit collects free cells from cells that are used after the check of the state of use of cells recently made by the full garbage collection unit, based on the check result of the state of use of cells. A full/partial control unit improves the process efficiency of parallel type garbage collection by making either the full garbage collection unit or the partial garbage collection unit perform a subsequent collection of free cells based on the state of collections made in the past.

Abstract: An interrupt processing apparatus is set if an interrupt factor occurs during execution of a moved instruction. The interrupt processing unit generates an interrupt single when processing after execution of a branch instruction proceeds towards an original location of the moved instruction, and resets when the processing after execution of the branch instruction proceeds in a direction different from the original location of the moved instruction.