Patents by Inventor Toshihiro Shiotsuki
Toshihiro Shiotsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8518744Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: GrantFiled: March 9, 2011Date of Patent: August 27, 2013Assignee: Renesas Electronics CorporationInventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Publication number: 20110159641Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Inventors: Takashi KIKUCHI, Koichi KANEMOTO, Chuichi MIYAZAKI, Toshihiro SHIOTSUKI
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Patent number: 7923292Abstract: In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: GrantFiled: July 29, 2010Date of Patent: April 12, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Publication number: 20100311205Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: ApplicationFiled: July 29, 2010Publication date: December 9, 2010Inventors: Takashi KIKUCHI, Koichi KANEMOTO, Chuichi MIYAZAKI, Toshihiro SHIOTSUKI
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Patent number: 7795741Abstract: A semiconductor device which stores a plurality of semiconductor chips, having planar sizes which differ, in the same sealing body in a state in which they are accumulated via an insulating film which has an adhesive property. In the semiconductor device, the thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit is formed is thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit is formed.Type: GrantFiled: September 7, 2007Date of Patent: September 14, 2010Assignee: Renesas Technology Corp.Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Publication number: 20080251897Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.Type: ApplicationFiled: September 7, 2007Publication date: October 16, 2008Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
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Patent number: 6916686Abstract: A contact collect is provided to prevent damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylidrical in outside shape, and a bottom part (suction head) thereof is made of soft synthetic rubber, etc. The protection tape pasted to the top surface of the semiconductor chip prevents the top surface of the semiconductor chip from directly contacting with the contact collect even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.Type: GrantFiled: January 15, 2003Date of Patent: July 12, 2005Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Wada, Kazunari Suzuki, Chuichi Miyazaki, Toshihiro Shiotsuki, Tomoko Higashino
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Publication number: 20050110127Abstract: A thin semiconductor device which assures a high production yield. The semiconductor device includes: first and second semiconductor chips each of which has electrodes over its first surface; first leads electrically connected with the electrodes of the first semiconductor chip through first bonding wires; second leads electrically connected with the electrodes of the second semiconductor chip through second bonding wires; a die pad with first and second surfaces opposite each other where the first semiconductor chip's first surface is bonded to the first surface and the second semiconductor chip's first surface is bonded to the second surface; and a resin sealer which seals the first and second semiconductor chips, inner portions of the first and second leads, the first and second bonding wires, and the die pad. The inner portions of the first and second leads and the die pad lie at the same height level in a thickness direction of the resin sealer.Type: ApplicationFiled: November 5, 2004Publication date: May 26, 2005Inventors: Kouichi Kanemoto, Kazunari Suzuki, Toshihiro Shiotsuki, Hideyuki Suga
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Patent number: 6610561Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.Type: GrantFiled: May 7, 2001Date of Patent: August 26, 2003Assignee: Hitachi, Ltd.Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki
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Publication number: 20030153127Abstract: Techniques are provided for preventing occurrence of damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip by use of a contact collet. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylindrical in outside shape, and a bottom part (suction head) thereof is made of a soft synthetic rubber, and so forth. The protection tape pasted to pasted to the top surface of the semiconductor chip can prevent the top surface of the semiconductor chip from coming in direct contact with the contact collet even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.Type: ApplicationFiled: January 15, 2003Publication date: August 14, 2003Applicant: Hitachi, Ltd. Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Wada, Kazunari Suzuki, Chuichi Miyazaki, Toshihiro Shiotsuki, Tomoko Higashino
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Patent number: 6445076Abstract: An insulating adhesive for electronic parts, which is to be used for bonding a semiconductor chip to a lead frame and comprises a resin and a solvent, the resin having (A) a weight average molecular weight (Mw) of 30,000 to 300,000 based on conversion into polystyrene and (B) a ratio of weight average molecular weight (Mw)/number average molecular weight (Mn) of 5 or less, and (C) the insulating adhesive for electronic parts having a viscosity of 5,000 to 100,000 mPa.s at a rotation number of 10 rpm and a viscosity ratio (&eegr;1 rpm/&eegr;10 rpm) of 1.0 to 6.0 as measured at 25° C. with an E-type viscometer.Type: GrantFiled: November 16, 2000Date of Patent: September 3, 2002Assignees: Hitachi Chemical Company, Ltd., Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takehiro Shimizu, Takafumi Dohdoh, Kazumi Tameshige, Hidekazu Matsuura, Yoshihiro Nomura, Kunihiro Tsubosaki, Toshihiro Shiotsuki, Kazunari Suzuki, Tomoko Higashino
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Patent number: 6335227Abstract: A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.Type: GrantFiled: October 18, 2000Date of Patent: January 1, 2002Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki
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Publication number: 20010016371Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.Type: ApplicationFiled: May 7, 2001Publication date: August 23, 2001Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki
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Patent number: 6137159Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.Type: GrantFiled: February 26, 1999Date of Patent: October 24, 2000Assignee: Hitachi, Ltd.Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki