Patents by Inventor Toshihiro Shiotsuki

Toshihiro Shiotsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8518744
    Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 27, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
  • Publication number: 20110159641
    Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Inventors: Takashi KIKUCHI, Koichi KANEMOTO, Chuichi MIYAZAKI, Toshihiro SHIOTSUKI
  • Patent number: 7923292
    Abstract: In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: April 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
  • Publication number: 20100311205
    Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.
    Type: Application
    Filed: July 29, 2010
    Publication date: December 9, 2010
    Inventors: Takashi KIKUCHI, Koichi KANEMOTO, Chuichi MIYAZAKI, Toshihiro SHIOTSUKI
  • Patent number: 7795741
    Abstract: A semiconductor device which stores a plurality of semiconductor chips, having planar sizes which differ, in the same sealing body in a state in which they are accumulated via an insulating film which has an adhesive property. In the semiconductor device, the thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit is formed is thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit is formed.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: September 14, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
  • Publication number: 20080251897
    Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.
    Type: Application
    Filed: September 7, 2007
    Publication date: October 16, 2008
    Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
  • Patent number: 6916686
    Abstract: A contact collect is provided to prevent damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylidrical in outside shape, and a bottom part (suction head) thereof is made of soft synthetic rubber, etc. The protection tape pasted to the top surface of the semiconductor chip prevents the top surface of the semiconductor chip from directly contacting with the contact collect even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: July 12, 2005
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Wada, Kazunari Suzuki, Chuichi Miyazaki, Toshihiro Shiotsuki, Tomoko Higashino
  • Publication number: 20050110127
    Abstract: A thin semiconductor device which assures a high production yield. The semiconductor device includes: first and second semiconductor chips each of which has electrodes over its first surface; first leads electrically connected with the electrodes of the first semiconductor chip through first bonding wires; second leads electrically connected with the electrodes of the second semiconductor chip through second bonding wires; a die pad with first and second surfaces opposite each other where the first semiconductor chip's first surface is bonded to the first surface and the second semiconductor chip's first surface is bonded to the second surface; and a resin sealer which seals the first and second semiconductor chips, inner portions of the first and second leads, the first and second bonding wires, and the die pad. The inner portions of the first and second leads and the die pad lie at the same height level in a thickness direction of the resin sealer.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 26, 2005
    Inventors: Kouichi Kanemoto, Kazunari Suzuki, Toshihiro Shiotsuki, Hideyuki Suga
  • Patent number: 6610561
    Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: August 26, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki
  • Publication number: 20030153127
    Abstract: Techniques are provided for preventing occurrence of damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip by use of a contact collet. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylindrical in outside shape, and a bottom part (suction head) thereof is made of a soft synthetic rubber, and so forth. The protection tape pasted to pasted to the top surface of the semiconductor chip can prevent the top surface of the semiconductor chip from coming in direct contact with the contact collet even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.
    Type: Application
    Filed: January 15, 2003
    Publication date: August 14, 2003
    Applicant: Hitachi, Ltd. Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Wada, Kazunari Suzuki, Chuichi Miyazaki, Toshihiro Shiotsuki, Tomoko Higashino
  • Patent number: 6445076
    Abstract: An insulating adhesive for electronic parts, which is to be used for bonding a semiconductor chip to a lead frame and comprises a resin and a solvent, the resin having (A) a weight average molecular weight (Mw) of 30,000 to 300,000 based on conversion into polystyrene and (B) a ratio of weight average molecular weight (Mw)/number average molecular weight (Mn) of 5 or less, and (C) the insulating adhesive for electronic parts having a viscosity of 5,000 to 100,000 mPa.s at a rotation number of 10 rpm and a viscosity ratio (&eegr;1 rpm/&eegr;10 rpm) of 1.0 to 6.0 as measured at 25° C. with an E-type viscometer.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 3, 2002
    Assignees: Hitachi Chemical Company, Ltd., Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takehiro Shimizu, Takafumi Dohdoh, Kazumi Tameshige, Hidekazu Matsuura, Yoshihiro Nomura, Kunihiro Tsubosaki, Toshihiro Shiotsuki, Kazunari Suzuki, Tomoko Higashino
  • Patent number: 6335227
    Abstract: A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: January 1, 2002
    Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki
  • Publication number: 20010016371
    Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
    Type: Application
    Filed: May 7, 2001
    Publication date: August 23, 2001
    Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki
  • Patent number: 6137159
    Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: October 24, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Tsubosaki, Masachika Masuda, Akihiko Iwaya, Atsushi Nakamura, Chikako Imura, Toshihiro Shiotsuki