Abstract: A data conversion device converts a series of digital signals into an analog signal. The device has a current selection circuit that can vary the direction and magnitude of the current it outputs and an integrating circuit that integrates the current supplied from the current selection circuit to output a voltage. The direction of the current is determined in accordance with the digital signals fed in. When the absolute value of the current is great, the value by which the absolute value of the current is increased is decreased, and the value by which the absolute value of the current is decreased is increased.

Abstract: A data conversion device for synthesizing digital data composed of two or more components (of which each consists of a series of one-bit digital data) so as to output a single analog signal has: a switch circuit for selecting one of the components of the digital data at a time by dividing a predetermined period into intervals having predetermined lengths of time in accordance with a select signal; a timing generator for generating the select signal; a current feeding circuit for feeding a current that flows in one or another direction in accordance with the output of the switch circuit; and a current-to-voltage conversion circuit for converting the current into a voltage so as to produce an analog signal.

Abstract: A circuit for controlling a rotating member is provided with an input capture register which reads out the value of a free running counter at a timing of an FG (frequency generated) pulse generated in accordance with a rotation of a rotating member. A central processing unit performs an interrupt operation based on a PG (phase generated) pulse generated in accordance with a rotation of the rotating member and an interrupt operation based on the FG pulse. A pulse width modulation circuit rotates the rotating member by use of a speed error signal and a phase error signal which are obtained by the interrupt operations of the central processing unit. A rotating member driver is also provided. The central processing unit calculates the phase error signal from an output of the input capture register based on an FG pulse generated after the generation of the PG pulse.