Abstract: The scan test circuit according to one embodiment of the present invention includes a noninversion/inversion control circuit inserted and connected between a sequential circuit and a combinational circuit included in a path to be subjected to a scan test, the noninversion/inversion control circuit not inverting or inverting scan data output from the sequential circuit, on outside of said sequential circuit at arbitrary timing.

Abstract: A semiconductor integrated circuit disclosed herein, comprises a first core which realizes a predetermined function; a second core which is different from the first core and realizes a predetermined function; a power supply circuit which is capable of supplying, to the first core, a power supply voltage different from that supplied to the second core; and a clock generating circuit which supplies a clock signal to each of the first core and the second core, the clock generating circuit including a clock skew reducing circuit which reduces clock skew occurring between the clock signal in the first core and the clock signal in the second core.

Abstract: The scan test circuit according to one embodiment of the present invention comprises a noninversion/inversion control circuit inserted and connected between a sequential circuit and a combinational circuit included in a path to be subjected to a scan test, the noninversion/inversion control circuit not inverting or inverting scan data output from said sequential circuit, on outside of said sequential circuit at arbitrary timing.

Abstract: A semiconductor integrated circuit disclosed herein, comprises a first core which realizes a predetermined function; a second core which is different from the first core and realizes a predetermined function; a power supply circuit which is capable of supplying, to the first core, a power supply voltage different from that supplied to the second core; and a clock generating circuit which supplies a clock signal to each of the first core and the second core, the clock generating circuit including a clock skew reducing circuit which reduces clock skew occurring between the clock signal in the first core and the clock signal in the second core.

Abstract: In the hold violation improvement method of the present invention, when a hold violation occurs in a path from a first sequential circuit (101) to a second sequential circuit (102) in a semiconductor integrated circuit, a timing analysis is performed for cells in the path from an input side in the path. A delay cell is inserted into the path so that the delay time of the path is over the worst delay time of the cell. The series of the above processes is repeated from the hold worst path having the worst hold violation to other paths having the hold violation, in order, without decreasing any time margin to avoid a setup violation.