Patents by Inventor Toshihiro Yagi
Toshihiro Yagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106348Abstract: A semiconductor integrated circuit includes a front stage circuit and a rear stage circuit. The rear stage circuit includes first, second, fifth, and sixth transistors and a plurality of seventh transistors. The front stage circuit includes first and second inverters and third and fourth transistors. The third transistor is between the first inverter and the rear stage circuit, and has a gate connected to a first power supply node. The fourth transistor is between the second inverter and the rear stage circuit, and has a gate connected to the first power supply node. A breakdown voltage of each of the third and fourth transistors in the front stage circuit is lower than that of the first, second, fifth, sixth, and seventh transistors in the rear stage circuit.Type: ApplicationFiled: September 1, 2023Publication date: March 28, 2024Inventor: Toshihiro YAGI
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Patent number: 11923843Abstract: A semiconductor device of an embodiment includes a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group; a first correction circuit configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group; a second correction circuit configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; and a control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit.Type: GrantFiled: March 10, 2021Date of Patent: March 5, 2024Assignee: Kioxia CorporationInventor: Toshihiro Yagi
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Patent number: 11843375Abstract: A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.Type: GrantFiled: October 19, 2022Date of Patent: December 12, 2023Assignee: Kioxia CorporationInventor: Toshihiro Yagi
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Patent number: 11742850Abstract: According to one embodiment, a data transmission device includes a buffer circuit configured to set a voltage level of a data signal to high or low, a power supply line for supplying a power supply voltage to the buffer circuit, a buffer control circuit configured to control a switching operation of the buffer circuit, a current circuit configured to make a dummy current flow to the power supply line, and a current control circuit configured to control the dummy current based on one of the set voltage level and a transmission timing of the data signal.Type: GrantFiled: August 3, 2020Date of Patent: August 29, 2023Assignee: Kioxia CorporationInventor: Toshihiro Yagi
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Publication number: 20230044191Abstract: A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.Type: ApplicationFiled: October 19, 2022Publication date: February 9, 2023Applicant: Kioxia CorporationInventor: Toshihiro YAGI
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Patent number: 11515877Abstract: A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.Type: GrantFiled: June 1, 2021Date of Patent: November 29, 2022Assignee: Kioxia CorporationInventor: Toshihiro Yagi
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Publication number: 20220182059Abstract: A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.Type: ApplicationFiled: June 1, 2021Publication date: June 9, 2022Applicant: Kioxia CorporationInventor: Toshihiro YAGI
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Publication number: 20220052689Abstract: A semiconductor device of an embodiment includes a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group; a first correction circuit configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group; a second correction circuit configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; and a control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit.Type: ApplicationFiled: March 10, 2021Publication date: February 17, 2022Applicant: Kioxia CorporationInventor: Toshihiro YAGI
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Patent number: 11211905Abstract: According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.Type: GrantFiled: August 28, 2019Date of Patent: December 28, 2021Assignee: Toshiba Memory CorporationInventors: Yohei Yasuda, Hidefumi Kushibe, Toshihiro Yagi
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Publication number: 20200366289Abstract: According to one embodiment, a data transmission device includes a buffer circuit configured to set a voltage level of a data signal to high or low, a power supply line for supplying a power supply voltage to the buffer circuit, a buffer control circuit configured to control a switching operation of the buffer circuit, a current circuit configured to make a dummy current flow to the power supply line, and a current control circuit configured to control the dummy current based on one of the set voltage level and a transmission timing of the data signal.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Inventor: Toshihiro YAGI
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Publication number: 20200266774Abstract: According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.Type: ApplicationFiled: August 28, 2019Publication date: August 20, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yohei YASUDA, Hidefumi KUSHIBE, Toshihiro YAGI
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Patent number: 10560084Abstract: According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.Type: GrantFiled: September 6, 2018Date of Patent: February 11, 2020Assignee: Toshiba Memory CorporationInventor: Toshihiro Yagi
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Publication number: 20190081622Abstract: According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.Type: ApplicationFiled: September 6, 2018Publication date: March 14, 2019Applicant: Toshiba Memory CorporationInventor: Toshihiro YAGI
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Publication number: 20180138907Abstract: According to one embodiment, a buffer circuit sets a level of transmission data to high or low, a power supply line supplies a power supply voltage to the buffer circuit, a buffer control circuit controls a switching operation of the buffer circuit, a current circuit feeds a dummy current to the power supply line, and a current control circuit controls the dummy current based on the level set in the transmission data.Type: ApplicationFiled: August 29, 2017Publication date: May 17, 2018Inventor: Toshihiro YAGI
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Patent number: 9617529Abstract: Disclosed is a method for production of recombinant human alpha-galactosidase A (rh alpha-Gal A) in a large scale, with a high purity. The method comprises the steps of (a) culturing rh alpha-Gal A-producing mammalian cells in a serum-free medium, (b) collecting culture supernatant, (c) subjecting the culture supernatant to anion-exchange column chromatography, (d) to hydrophobic column chromatography, (e) to a column chromatography employing as solid phase a material having affinity for phosphate group, (f) to cation-exchange column chromatography, and (g) to gel filtration column chromatography, in the order.Type: GrantFiled: July 24, 2013Date of Patent: April 11, 2017Assignee: JCR PHARMACEUTICALS CO., LTD.Inventors: Masahiro Asano, Toshihiro Yagi, Tsuyoshi Fukui, Atsuko Kawasaki, Yukichi Hatano, Kazutoshi Mihara, Atsushi Sugimura
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Publication number: 20150210992Abstract: Disclosed is a method for production of recombinant human alpha-galactosidase A (rh alpha-Gal A) in a large scale, with a high purity. The method comprises the steps of (a) culturing rh alpha-Gal A-producing mammalian cells in a serum-free medium, (b) collecting culture supernatant, (c) subjecting the culture supernatant to anion-exchange column chromatography, (d) to hydrophobic column chromatography, (e) to a column chromatography employing as solid phase a material having affinity for phosphate group, (f) to cation-exchange column chromatography, and (g) to gel filtration column chromatography, in the order.Type: ApplicationFiled: July 24, 2013Publication date: July 30, 2015Inventors: Masahiro Asano, Toshihiro Yagi, Tsuyoshi Fukui, Atsuko Kawasaki, Yukichi Hatano, Kazutoshi Mihara, Atsushi Sugimura