Patents by Inventor Toshihisa Hyakudai
Toshihisa Hyakudai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146654Abstract: There is provided a transmission apparatus that transmits information generated by an information source and divided for each block to a transmission path in units of frames including a plurality of the blocks, including: a transmission unit that stops the transmission of information to the transmission path or transmits toggle data to the transmission path in one of several blocks in the frame where an amount of information to be transmitted is less than a transmission capacity of the transmission path, the toggle data having a cycle of transition of information longer than that of information in a block other than the one block in the frame.Type: ApplicationFiled: January 12, 2024Publication date: May 2, 2024Inventors: Satoshi Ota, Toshihisa Hyakudai
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Publication number: 20240146494Abstract: [Object] Transmission efficiency is improved while transmission latency is minimized as possible. [Solving Means] A communication apparatus includes a communication section configured to count an interval allocated in a TDD (Time Division Duplex) mode as one TDD time slot, with a plurality of the TDD time slots counted as one period, the communication section further transmitting periodically, to a communication partner apparatus, multiple application packets corresponding to multiple serial signals generated by multiple applications, and a transmission control section configured to provide, from among the multiple TDD time slots, at least one specific TDD time slot for transmitting a limited portion of the application packets corresponding to at least two of the multiple applications, the transmission control section further shifting, in each period, priorities of the limited portion of the application packets to be transmitted in the specific TDD time slot.Type: ApplicationFiled: February 18, 2022Publication date: May 2, 2024Inventors: Toshihisa Hyakudai, Satoshi Ota, Junya Yamada
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Patent number: 11971842Abstract: A communication device includes a communication unit configured to transmit a serial signal group conforming to a serial peripheral interface (SPI) and transmitted from a master in synchronization with a clock to a communication partner device as a batch of data blocks within one frame period of a predetermined communication protocol, or transmit the serial signal group to the communication partner device as a plurality of data blocks divided according to a plurality of frame periods.Type: GrantFiled: August 18, 2021Date of Patent: April 30, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
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Patent number: 11960434Abstract: A communication device includes: a communication unit that adds, to a set of data blocks including a serial signal group conforming to SPI transmitted from a master in synchronization with a clock, identification information for identifying the data blocks, and transmits the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or adds, to data blocks each including a part of the serial signal group, identification information for identifying each of the data blocks, and transmits the data blocks to the communication partner device in a plurality of frame periods; and a storage unit that sequentially stores a predetermined number of data blocks transmitted from the master and outputs a data block transmitted from the communication partner device in response to the predetermined number of data blocks from the master and stored, to transmit the data block to the master.Type: GrantFiled: April 5, 2022Date of Patent: April 16, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
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Patent number: 11962329Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.Type: GrantFiled: June 30, 2020Date of Patent: April 16, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Tatsuya Sugioka, Toshihisa Hyakudai, Masayuki Unuma, Daisuke Okazawa, Aritoshi Kimura, Hiroshi Shiroshita
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Publication number: 20240089074Abstract: Communication apparatus with correct audio signal regeneration are disclosed. In one example, a communication apparatus includes a counter that counts the number of a predetermined reference clock included in one cycle of a divided signal of an audio master clock with a frequency that is equal to a product of a frequency of a sampling clock for sampling of an audio signal and a multiplier on the basis of the audio master clock, a ratio of division of the divided signal and the predetermined reference clock. A packet generator generates a packet including the counted number counted, a bit width of SD (Serial Data) conforming to an I2S standard, the frequency of the sampling clock, the ratio of division of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.Type: ApplicationFiled: February 3, 2022Publication date: March 14, 2024Inventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
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Publication number: 20240078210Abstract: [Object] To perform serial communication at high speed by combining different communication methods with each other. [Solving Means] A communication apparatus includes a communicating unit configured to add identification information identifying a data block to one set of the data block including a serial signal group, the serial signal group being transmitted from a master in synchronism with a clock and complying with SPI (Serial Peripheral Interface), and transmit the one set of the data block to a communication partner apparatus within one frame period of a predetermined communication protocol, or add identification information identifying each of multiple data blocks to the multiple data blocks each including a part of the serial signal group and transmit the multiple data blocks to the communication partner apparatus in multiple frame periods.Type: ApplicationFiled: February 3, 2022Publication date: March 7, 2024Inventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
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Patent number: 11902162Abstract: There is provided a transmission apparatus that transmits information generated by an information source and divided for each block to a transmission path in units of frames including a plurality of the blocks, including: a transmission unit that stops the transmission of information to the transmission path or transmits toggle data to the transmission path in one of several blocks in the frame where an amount of information to be transmitted is less than a transmission capacity of the transmission path, the toggle data having a cycle of transition of information longer than that of information in a block other than the one block in the frame.Type: GrantFiled: April 8, 2021Date of Patent: February 13, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Satoshi Ota, Toshihisa Hyakudai
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Patent number: 11863500Abstract: A communication apparatus includes: a communication unit that periodically transmits, with an interval assigned by TDD (Time Division Duplex) being one TDD time slot and a plurality of TDD time slots being one period, a plurality of application packets corresponding to a plurality of serial signals generated by a plurality of applications to a communication partner device; and a transmission control unit that changes, for every one period, a priority of part of application packets corresponding to part of two or more applications of the plurality of applications, the part of application packets being transmitted in at least one specific TDD time slot for transmitting the part of application packets, the plurality of TDD time slots including the at least one specific TDD time slot.Type: GrantFiled: November 29, 2021Date of Patent: January 2, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Toshihisa Hyakudai, Satoshi Ota, Junya Yamada
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Publication number: 20230385225Abstract: The memory capacity for storing address information etc. of an I2C communication instrument, as well as the number of encoders and decoders can be reduced. A communication device to establish communication between a first I2C communication instrument and a second I2C communication instrument connected to a communication partner device, includes: an encoder that generates Header Packet Data including a target ID of the communication partner device and I2C Packet Data including a slave address and an offset address of the second I2C communication instrument; a communication unit that transmits a transmission packet including the Header Packet Data and the I2C Packet Data generated by the encoder to the communication partner device by a TDD communication scheme and receives a reception packet from the communication partner device by the TDD communication scheme; and a decoder that generates the I2C Packet Data from the reception packet.Type: ApplicationFiled: May 19, 2023Publication date: November 30, 2023Inventors: Junya Yamada, Toshihisa Hyakudai, Satoshi Ota
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Patent number: 11831739Abstract: A communication apparatus includes: a LINK for performing protocol-conversion on a signal from a Master and outputting the converted signal to a Slave SerDes and for performing protocol-conversion on a signal from the Slave SerDes and outputting the converted signal to the Master, the LINK being capable of alternatively selecting a first mode and a second mode when transmitting the signal from the Master to the Slave SerDes, in the first mode, the LINK converting the signal transmitted from the Master into a signal of a first communication standard in units of one byte, receiving a signal of the first communication standard including one of an ACK signal representing an affirmative response and a NACK signal representing a negative response after transmitting the converted signal to the Slave SerDes, converting the received signal into a signal of a second communication standard, and transmitting the converted signal to the Master.Type: GrantFiled: April 27, 2021Date of Patent: November 28, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Junya Yamada, Satoshi Ota, Toshihisa Hyakudai
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Publication number: 20230344552Abstract: To solve a problem related to error correction. A communication apparatus includes: a PHY that receives a first transmission signal conforming to a predetermined communication protocol from a communication partner apparatus and performs error correction on a plurality of first packets included in the first transmission signal; and a LINK that separates the plurality of first packets after error correction and generates a second packet including error correction impossible information of the first packet on which the error correction has not been correctly performed, and the PHY transmits a second transmission signal including the second packet to the communication partner apparatus.Type: ApplicationFiled: January 24, 2023Publication date: October 26, 2023Inventors: Junya Yamada, Toshihisa Hyakudai, Satoshi Ota
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Publication number: 20230308210Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. There are provided: a calculation section dividing inputted data into N bits to calculate a first running disparity of a data string of the N bits; a determination section determining whether the data string of the N bits is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated at a time point before the first running disparity; and an addition section inverting or non-inverting the data string of the N bits based on a result of the determination by the determination section to add a flag indicating the result of the determination by the determination section for outputting. The technology is applicable to a device communicating in an SLVS-EC specification.Type: ApplicationFiled: June 29, 2020Publication date: September 28, 2023Inventors: Tatsuya Sugioka, Toshihisa Hyakudai, Masayuki Unuma, Daisuke Okazawa, Aritoshi Kimura, Hiroshi Shiroshita
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Patent number: 11743024Abstract: Communication devices and systems with correct regeneration of an audio signal are disclosed. In one example, a communication device measures a number of predetermined reference clocks included in one cycle of a frequency divided signal, on the basis of an audio master clock having a frequency obtained by multiplying a frequency of a sampling clock to sample an audio signal, a frequency division ratio of a frequency divided signal of the audio master clock, and a predetermined reference clock. A packet generator generates a packet including information including the measured number, a bit width of serial data (SD) conforming to an Inter-IC Sound (I2S) standard, the frequency of the sampling clock, a frequency division ratio of the frequency divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.Type: GrantFiled: November 29, 2021Date of Patent: August 29, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
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Publication number: 20230269062Abstract: Communication apparatus and systems are disclosed. In one example, a communication apparatus, which sends and receives information to and from a communication partner apparatus alternately within a period allocated by a TDD communication scheme, includes a PHY, a LINK, decoders and encoders. The PHY receives a first transmission signal conforming to a predetermined communication protocol from the communication partner apparatus, performs error correction on first packets therein, and sends a second transmission signal to the communication partner apparatus. The LINK separates the first packets and aggregates second packets included in the second transmission signal to send the aggregated second packets to the PHY. The decoders decode the first packets. The encoders generate the second packets. The PHY stores error information regarding each of the decoders and the encoders, and includes an operation-administration-maintenance (OAM) unit that includes the error information in one of the second packets.Type: ApplicationFiled: February 15, 2023Publication date: August 24, 2023Inventors: Junya Yamada, Toshihisa Hyakudai, Satoshi Ota
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Publication number: 20230254059Abstract: A communication apparatus includes: an encoder that generates a packet of a time division duplex (TDD) communication system, the packet including a high-definition multimedia interface (HDMI) signal; and a communication unit that transmits the packet to a communication partner device for each of a plurality of divided periods obtained by dividing one TDD burst period in the TDD communication system.Type: ApplicationFiled: January 24, 2023Publication date: August 10, 2023Inventors: Toshihisa Hyakudai, Satoshi Ota, Junya Yamada
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Publication number: 20230254100Abstract: A communication apparatus includes: a communication unit that performs signal transmission to and from a communication partner apparatus; and a communication control unit that changes a signal ratio in a first direction to the communication partner apparatus and a signal ratio in a second direction from the communication partner apparatus in accordance with a signal transmission state with the communication partner apparatus.Type: ApplicationFiled: March 4, 2021Publication date: August 10, 2023Inventors: Toshihisa Hyakudai, Hiroo Takahashi, Junya Yamada
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Publication number: 20230205722Abstract: Communication devices and systems are disclosed. In one example, a communication device includes a LINK that performs protocol conversion of a signal from a Master and outputs the converted signal to a Slave SerDes, and of a signal from the Slave SerDes and outputs the converted signal to the Master. The LINK alternatively selects a first mode and a second mode. In the first mode, the LINK converts a 1-byte signal transmitted from the Master into a signal of a first communication standard in units of the 1-byte signal and transmits the converted signal to the Slave SerDes, then receives a signal of the first communication standard including an ACK signal representing an acknowledgement or a NACK signal representing a negative acknowledgement, and converts the received signal into a signal of a second communication standard and transmits the converted signal to the Master.Type: ApplicationFiled: June 4, 2021Publication date: June 29, 2023Inventors: Junya Yamada, Satoshi Ota, Toshihisa Hyakudai
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Patent number: 11669484Abstract: [Overview] [Problem to be Solved] To provide a communication device and a communication system that each enable transmission of a command and data of I3C in a protocol different from the I3C. [Solution] A communication device according to a first aspect of the present disclosure includes: an I3C device section that generates a command and data of I3C; and a communication device section that transmits the command and data of the I3C to another communication device via a bus by using a payload in a protocol different from the I3C.Type: GrantFiled: March 13, 2020Date of Patent: June 6, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Toshihisa Hyakudai, Hiroo Takahashi, Takayuki Hirama
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Publication number: 20230146989Abstract: In one example, a communication device includes a LINK that generates a first output signal on a basis of a first external signal from a first external device, outputs the first output signal to a second external device, generates a second output signal on a basis of a second external signal from the second external device, and outputs the second output signal to the first external device, in which each of the first output signal and the second external signal includes command information indicating content of a command transmitted from the first external device, final-destination-device-identification-information for identifying a final destination device of data transmitted from the first external device, internal address information indicating an internal address of the final destination device, data length information indicating a length of the data transmitted from the first external device, and data-end-position-information indicating an end position of the data transmitted.Type: ApplicationFiled: March 11, 2021Publication date: May 11, 2023Inventors: Takayuki Hirama, Junya Yamada, Hiroo Takahashi, Toshihisa Hyakudai