Patents by Inventor Toshihisa Tsukada

Toshihisa Tsukada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9392898
    Abstract: A folding hanger includes of a pair of arms and a hook. Above-mentioned pair of arms and the hook have a common axis of rotation and each arm of the arms is structured by two parallel boards and an intermediate board connecting the two parallel boards. An angle between the center line of the arm and an edge line, which passes through the common axis of rotation and an edge of the intermediate board, is set between 50 degrees and 80 degrees.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 19, 2016
    Assignee: CUBE IT LIMITED
    Inventor: Toshihisa Tsukada
  • Publication number: 20160120350
    Abstract: A folding hanger includes of a pair of arms and a hook. Above-mentioned pair of arms and the hook have a common axis of rotation and each arm of the arms is structured by two parallel boards and an intermediate board connecting the two parallel boards. An angle between the center line of the arm and an edge line, which passes through the common axis of rotation and an edge of the intermediate board, is set between 50 degrees and 80 degrees.
    Type: Application
    Filed: March 7, 2013
    Publication date: May 5, 2016
    Inventor: Toshihisa TSUKADA
  • Patent number: 6483660
    Abstract: A magnetic disk unit of form factor size with a low power consumption, a short average seek time and a high performance. The unit includes at least two spindles for supporting and rotating magnetic disks. Specifically, two 1.3-inch disks, three 1.0-inch disks or four 0.7-inch disks are arranged in a housing originally intended for a 1.8-inch magnetic disk. The unit further includes a device for writing and reading information while selecting a spindle. The card-type disk unit thus can be reduced in thickness, with a smaller power consumption for starting the disk rotation and further with an improved average seek velocity.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: November 19, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kyo Akagi, Toshihisa Tsukada, Yoshihiro Shiroishi
  • Patent number: 5889573
    Abstract: The present invention concerns an active-matrix addressed TFT substrate using a thin film transistor, a manufacturing method and an anodic oxidation method thereof, a liquid crystal display panel using the TFT substrate and a liquid crystal display equipment using the liquid crystal display panel and, more in particular, it relates to a structure and a manufacturing method which enables to improve the characteristics thereof.In the present invention, Cr or Ta is used for gate terminals, aluminum or a metal mainly composed of aluminum is used for gate bus-lines extended therefrom, gate electrodes and thin film capacitances (additional capacitance, storage capacitance) and an anodic oxidized film composed of the metal and free from defect is used for at least one of gate insulators, dielectric films of the thin film capacitances and interlayer insulation films for the intersections between the bus-lines.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: March 30, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Yasuo Tanaka, Ken Tsutsui, Toshihisa Tsukada, Kazuo Shirahashi, Akira Sasano, Yuka Matsukawa
  • Patent number: 5854997
    Abstract: An electronic interpreter for interpreting sentences between a first person and a second person. The electronic interpreter includes a memory for storing sentence data in a data structure having a plurality of sets of sentences including translations of the sentences, wherein each sentence of each set of sentences is linked to another of the sets of sentences, and a data processing unit.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: December 29, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hiroko Sukeda, Yoshiyuki Kaneko, Tetsuya Nakagawa, Muneaki Yamaguchi, Toshihisa Tsukada
  • Patent number: 5761352
    Abstract: An optical switch has an input optical waveguide and an output optical waveguide that are physically and optically separated from each other by a two-level crossing arrangement. The direction of optical signal propagation is switchable by a connecting optical waveguide to provide optical coupling between the input and output optical waveguides. Crosstalk and loss due to diffraction at each crossing are small, and insertion loss does not increase, even for a large-scale application.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: June 2, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Shigeki Kitajima, Hideaki Takano, Toshihisa Tsukada, Hiroaki Inoue
  • Patent number: 5719408
    Abstract: In the present invention, Cr or Ta is used for gate terminals, aluminum or a metal mainly composed of aluminum is used for gate bus-lines extended therefrom, gate electrodes and thin film capacitances (additional capacitance, storage capacitance) and an anodic oxidized film composed of the metal and free from defect is used for at least one of gate insulators, dielectric films of the thin film capacitances and interlayer insulation films for the intersections between the bus-lines. In a more preferred structure, the anodic oxidized film is used for all of the gate insulators, the dielectric films for the thin film capacitances and the interlayer insulation films for the intersections between the bus lines. The present invention also relates to a method of selectively forming an anodic oxidized film on an aluminum pattern. That is, in a case of forming a selective oxidation mask to a desired region on the aluminum pattern with a positive type photoresist, in the present invention, an angle (.theta.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: February 17, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Yasuo Tanaka, Ken Tsutsui, Toshihisa Tsukada, Kazuo Shirahashi, Akira Sasano, Yuka Matsukawa
  • Patent number: 5672523
    Abstract: The present invention concerns an active-matrix addressed TFT substrate using a thin film transistor, a manufacturing method and an anodic oxidation method thereof, a liquid crystal display panel using the TFT substrate and a liquid crystal display equipment using the liquid crystal display panel. Cr or Ta is used for gate terminals; aluminum or a metal composed mainly of aluminum is used for gate bus-lines extended therefrom, gate electrodes and thin film capacitances (additional capacitance, storage capacitance); and an anodic oxidized film composed of the metal and free from defect is used for at least one of gate insulators, dielectric films of the thin film capacitances and interlayer insulation films for the intersections between the bus-lines. In forming a selective oxidation mask to a desired region on the aluminum pattern with a positive type photoresist, for the anodic oxidation, an angle (.theta.) formed between the selective oxidation mask and the aluminum pattern is made as: .beta..gtoreq.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: September 30, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Yasuo Tanaka, Ken Tsutsui, Toshihisa Tsukada, Kazuo Shirahashi, Akira Sasano, Yuka Matsukawa
  • Patent number: 5604142
    Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: February 18, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
  • Patent number: 5585290
    Abstract: The present invention concerns an active-matrix addressed TFT substrate using a thin film transistor, a manufacturing method and an anodic oxidation method thereof, a liquid crystal display panel using the TFT substrate and a liquid crystal display equipment using the liquid crystal display panel and, more in particular, it relates to a structure and a manufacturing method which enables to improve the characteristics thereof. In the present invention, Cr or Ta is used for gate terminals, aluminum or a metal mainly composed of aluminum is used for gate bus-lines extended therefrom, gate electrodes and thin film capacitances (additional capacitance, storage capacitance) and an anodic oxidized film composed of the metal and free from defect is used for at least one of gate insulators, dielectric films of the thin film capacitances and interlayer insulation films for the intersections between the bus-lines.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: December 17, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Yasuo Tanaka, Ken Tsutsui, Toshihisa Tsukada, Kazuo Shirahashi, Akira Sasano, Yuka Matsukawa
  • Patent number: 5359206
    Abstract: Disclosed is an active-matrix addressed TFT substrate using a thin film transistor, a manufacturing method and an anodic oxidation method thereof, a liquid crystal display panel using the TFT substrate and a liquid crystal display equipment using the liquid crystal display panel. In the TFT substrate, Cr or Ta is used for gate terminals, aluminum or a metal mainly composed of aluminum is used for gate bus-lines extending therefrom, for gate electrodes, and for electrodes of thin film capacitors (additional capacitance, storage capacitance), and an anodic oxidized film composed of the metal and free from defect is used for at least one of gate insulators, dielectric films of the thin film capacitances and interlayer insulating films for the intersections between the bus-lines. Also disclosed is a method of selectively forming an anodic oxidized film on an aluminum pattern.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: October 25, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Haruo Matsumaru, Yasuo Tanaka, Ken Tsutsui, Toshihisa Tsukada, Kazuo Shirahashi, Akira Sasano, Yuka Matsukawa
  • Patent number: 5340760
    Abstract: This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: August 23, 1994
    Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
  • Patent number: 5266825
    Abstract: A thin-film transistor using hydrogenated amorphous silicon (a-Si:H), and particularly a thin-film device such as a thin-film transistor having high conductivity, large drivability and high process margin, and a display panel using the same transistors. The object of the invention is to reduce defects due to shorts between the gate and the source or between the gate and the drain, to prevent signal line defect even in case defects develop due to shorts, and to expand the design margin and process margin in the array. A capacity is connected to the gate electrode of the channel side and a voltage is applied to the gate electrode via the capacity.
    Type: Grant
    Filed: April 7, 1992
    Date of Patent: November 30, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshihisa Tsukada, Yoshiyuki Kaneko
  • Patent number: 5200634
    Abstract: A thin film phototransistor is provided having a field effect transistor structure where at least one end of the gate electrode is not overlapped with an electrode neighboring the end. Such a thin film phototransistor has: (1) a function as a photosensor and a switching function; (2) a high input impedance; (3) a voltage control function; and (4) a high photocurrent ON/OFF ratio. This thin film phototransistor can be used independently or together with a thin film transistor for picture elements of a one-dimensional or two-dimensional photosensor array, producing satisfactory results.
    Type: Grant
    Filed: December 9, 1991
    Date of Patent: April 6, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshihisa Tsukada, Yoshiyuki Kaneko, Hideaki Yamamoto, Norio Koike, Ken Tsutsui, Haruo Matsumaru, Yasuo Tanaka
  • Patent number: 5189497
    Abstract: This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.
    Type: Grant
    Filed: September 24, 1991
    Date of Patent: February 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
  • Patent number: 5153690
    Abstract: A thin-film transistor using hydrogenated amorphous silicon (a-Si:H), and particularly a thin-film device such as a thin-film transistor having high conductivity, large drivability and high process margin, and a display panel using the same transistors. The object of the invention is to reduce defects due to shorts between the gate and the source or between the gate and the drain, to prevent signal line defect even in case defects develop due to shorts, and to expand the design margin and process margin in the array. A capacity is connected to the gate electrode of the channel side and a voltage is applied to the gate electrode via the capacity.
    Type: Grant
    Filed: October 15, 1990
    Date of Patent: October 6, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Toshihisa Tsukada, Yoshiyuki Kaneko
  • Patent number: 5151385
    Abstract: A semiconductor device such as a solar cell, photodiode and solid state imaging device comprises a semiconductor layer made of amorphous silicon formed on a given substrate, and a transparent conductive layer formed by an interfacial reaction between the amorphous silicon and a metallic film directly formed on the amorphous silicon. This transparent conductive layer is used as a transparent electrode of the device and if necessary the remainder after having partially removed the metallic film for the transparent conductive layer is used as a conductive layer and light shielding film.
    Type: Grant
    Filed: October 3, 1988
    Date of Patent: September 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Yamamoto, Koichi Seki, Toshihiro Tanaka, Akira Sasano, Toshihisa Tsukada, Yasuharu Shimomoto, Toshio Nakano, Hideto Kanamori
  • Patent number: 5130773
    Abstract: A photosensor with improved performance is provided with a gate electrode structure for a field effect transistor that includes a semiconductor layer photosensitivity. The gate electrode can be constituted with a kind of metal or a low resistance semiconductor in conjunction with a semiconductor area with photosensitivity adjacent thereto. As a photosensitive semiconductor, amorphous silicon can be used because of its comparatively easy manufacturing method and its high sensitivity. As a field effect transistor, a thin film transistor of amorphous silicon can be used to correspond to the demand for making transistors over a large area. A MOSFET is preferably used as a field effect transistor for the improvement of sensitivity and speed of the sensor.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: July 14, 1992
    Assignee: Hitachi, Ltd.
    Inventor: Toshihisa Tsukada
  • Patent number: 5079603
    Abstract: This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.
    Type: Grant
    Filed: April 30, 1990
    Date of Patent: January 7, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Komori, Satoshi Meguro, Takaaki Hagiwara, Hitoshi Kume, Toshihisa Tsukada, Hideaki Yamamoto
  • Patent number: 5032531
    Abstract: In a first manufacturing step of an active matrix liquid-crystal panel, a transparent conductor film and a metal film are sequentially accumulated on a substrate in this order so as to form a two-layer film. The two-layer film including the transparent conductor film and the metal film is subjected to photoetching to simultaneously form at least a pixel electrode (transparent conductor film) and a gate electrode (metal film) of a thin-film transistor according to a predetermined pattern. In a fabrication process near the end of the fabrication, when the source and drain electrodes of the thin-film transistors are formed, the metal film on the pixel electrode is simultaneously removed. Since the removal of the metal film protecting the pixel electrode is simultaneously achieved at a point near the final process, protection of the pixel electrode is guaranteed, thereby realizing improvement of the yielding and reduction of the production process.
    Type: Grant
    Filed: July 7, 1989
    Date of Patent: July 16, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Ken Tsutsui, Toshihisa Tsukada, Hideaki Yamamoto, Yasuo Tanaka, Haruo Matsumaru