Patents by Inventor Toshihito Habuka
Toshihito Habuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8538364Abstract: Gain setting can be performed at high speed while reducing DC offset due to a filter cutoff frequency changeover without the need for input signal muting. A filter circuit having first and second filters is capable of allowing settings of first and second cutoff frequencies. First and second filter switch circuits and a charging circuit including a charging resistor and a charging switch are provided. For a first time period, the first switch circuit is controllably turned on while the second switch circuit is controllably turned off, thereby providing the first filter function. For a second time period, the first switch circuit is controllably turned off while the second switch circuit is controllably turned on, thereby providing the second filter function. For the first time period, the charging switch is controllably turned on so that the second capacitor is charged via the charging resistor.Type: GrantFiled: May 28, 2010Date of Patent: September 17, 2013Assignee: Renesas Electronics CorporationInventors: Yusaku Katsube, Junichi Takahashi, Masaaki Yamada, Toshihito Habuka, Kenichi Shibata, Fumihito Yamaguchi
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Patent number: 8229384Abstract: A filter circuit includes first capacitors, second capacitors capable of altering a cutoff frequency by being connected in parallel with the first capacitors, first switches for connecting the second capacitors in parallel with the first capacitors, and charging circuits for the second capacitors. The charging circuits include second switches, and resistances for attenuating the amplitudes of input voltages to be fed to the second capacitors, by being connected in series with the second capacitors. The second capacitors are charged through the resistances in a state where the first switches are turned OFF and where the second switches are turned ON. Thus, a DC offset which is ascribable to the cutoff frequency switching of a filter is reduced.Type: GrantFiled: April 7, 2009Date of Patent: July 24, 2012Assignee: Renesas Electronics CorporationInventors: Masaaki Yamada, Yusaku Katsube, Junichi Takahashi, Toshihito Habuka, Fumihito Yamaguchi
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Patent number: 7961821Abstract: A D.C. offset canceling and gain adjusting techniques permitting completion of correction of D.C. offsets and gain adjustment of amplifiers for amplifying reception signals in a radio communication system are provided. A communication semiconductor integrated circuit has a plurality of low-pass filters and variable gain amplifiers which are alternately connected in multiple stages, and high gain amplifier circuits for amplifying reception signals to a predetermined amplitude level. Offset cancellation values are generated by detecting D.C. offsets of amplifiers for amplifying reception signals according to a set gain, and stored into a memory, and read out of the memory to cancel the D.C. offsets of the amplifiers when starting reception and altering the gain. Gain setting in a high gain amplifying section is accomplished using rough and precise settings.Type: GrantFiled: November 24, 2008Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventors: Toshihito Habuka, Naoto Inokawa, Kiyoharu Ozaki, Tatsuji Matsuura, Koichi Yahagi
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Publication number: 20110026507Abstract: Gain setting can be performed at high speed while reducing DC offset due to a filter cutoff frequency changeover without the need for input signal muting. A filter circuit having first and second filters is capable of allowing settings of first and second cutoff frequencies. First and second filter switch circuits and a charging circuit including a charging resistor and a charging switch are provided. For a first time period, the first switch circuit is controllably turned on while the second switch circuit is controllably turned off, thereby providing the first filter function. For a second time period, the first switch circuit is controllably turned off while the second switch circuit is controllably turned on, thereby providing the second filter function. For the first time period, the charging switch is controllably turned on so that the second capacitor is charged via the charging resistor.Type: ApplicationFiled: May 28, 2010Publication date: February 3, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yusaku KATSUBE, Junichi TAKAHASHI, Masaaki YAMADA, Toshihito HABUKA, Kenichi SHIBATA, Fumihito YAMAGUCHI
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Publication number: 20090258626Abstract: A filter circuit includes first capacitors, second capacitors capable of altering a cutoff frequency by being connected in parallel with the first capacitors, first switches for connecting the second capacitors in parallel with the first capacitors, and charging circuits for the second capacitors. The charging circuits include second switches, and resistances for attenuating the amplitudes of input voltages to be fed to the second capacitors, by being connected in series with the second capacitors. The second capacitors are charged through the resistances in a state where the first switches are turned OFF and where the second switches are turned ON. Thus, a DC offset which is ascribable to the cutoff frequency switching of a filter is reduced.Type: ApplicationFiled: April 7, 2009Publication date: October 15, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Masaaki YAMADA, Yusaku KATSUBE, Junichi TAKAHASHI, Toshihito HABUKA, Fumihito YAMAGUCHI
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Publication number: 20090080577Abstract: A D.C. offset canceling and gain adjusting techniques permitting completion of correction of D.C. offsets and gain adjustment of amplifiers for amplifying reception signals in a radio communication system are provided. A communication semiconductor integrated circuit has a plurality of low-pass filters and variable gain amplifiers which are alternately connected in multiple stages, and high gain amplifier circuits for amplifying reception signals to a predetermined amplitude level. Offset cancellation values are generated by detecting D.C. offsets of amplifiers for amplifying reception signals according to a set gain, and stored into a memory, and read out of the memory to cancel the D.C. offsets of the amplifiers when starting reception and altering the gain. Gain setting in a high gain amplifying section is accomplished using rough and precise settings.Type: ApplicationFiled: November 24, 2008Publication date: March 26, 2009Inventors: Toshihito HABUKA, Naoto INOKAWA, Kiyoharu OZAKI, Tatsuji MATSUURA, Koichi YAHAGI
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Patent number: 7471748Abstract: A D.C. offset canceling technique and a gain adjusting technique permitting completion of correction of D.C. offsets and gain adjustment of amplifiers for amplifying reception signals in a relatively short period of time in a radio communication system, such as a wireless LAN, are to be provided. A communication semiconductor integrated circuit (high frequency IC) has a plurality each of low-pass filters and variable gain amplifiers which are alternately connected in multiple stages, and high gain amplifier circuits for amplifying reception signals to a predetermined amplitude level while eliminating unnecessary waves. Offset cancellation values are generated by detecting in advance D.C. offsets of amplifiers for amplifying reception signals according to a set gain, and stored into a memory, and read out of the memory to cancel the D.C. offsets of the amplifiers at the time of starting reception and altering the gain.Type: GrantFiled: May 28, 2004Date of Patent: December 30, 2008Assignee: Renesas Technology Corp.Inventors: Toshihito Habuka, Naoto Inokawa, Kiyoharu Ozaki, Tatsuji Matsuura, Koichi Yahagi
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Patent number: 7313125Abstract: The invention comprises: processing for receiving an OFDM packet having a preamble and the following data transmission symbol, in which packet the subcarrier interval of the preamble is set wider than that of the data transmission symbol; processing for estimating a DC offset occurring at a receiving side by using the received preamble; processing for correcting the DC offset on the received data transmission symbol, according to the estimation result of the DC offset; and processing for demodulating the DC offset corrected data transmission symbol. Thus, it is possible to estimate a DC offset and then correct the DC offset according to the estimated value, in the OFDM packet with no nul symbol defined there.Type: GrantFiled: March 26, 2004Date of Patent: December 25, 2007Assignee: Renesas Technology Corp.Inventors: Toyokazu Hori, Hiroshi Nogami, Toshihito Habuka, Naoto Inokawa, Kazuyuki Takada
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Patent number: 7263145Abstract: A wireless LAN system has auto gain control with no work load applied to its baseband processing block. When the wireless LAN system gets ready to receive a signal, the gain control circuit switches between the receiving antennas. The gain control circuit sets gain setting value time divisional data according to the level of a received signal to roughly control the gain to be set in the LAN and the gain to be set in two programmable gain amplifiers.Type: GrantFiled: July 14, 2003Date of Patent: August 28, 2007Assignee: Hitachi, Ltd.Inventors: Toshihito Habuka, Masaki Noda, Hiroshi Nogami, Toyokazu Hori, Tatsuji Matsuura, Kazuaki Hori, Naoto Inokawa
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Publication number: 20050159148Abstract: In a radio communication system having a plurality of antennas, a reception-system circuit including variable gain amplification circuits for amplifying a signal received from either of the antennas and a frequency conversion circuit for down-converting the received signal to a signal of a lower frequency, and a signal measuring circuit for detecting intensity of the received signal, whereby a signal received by either of the antennas is selected in accordance with a reception state and amplified and demodulated, change rates with time of a signal which is formed by the signal measuring circuit are determined in respect of either of the signals received by the plurality of antennas and a control signal for selecting a reception antenna is generated in accordance with a differences between the change rates.Type: ApplicationFiled: January 12, 2005Publication date: July 21, 2005Inventors: Toshihito Habuka, Naoto Inokawa, Tatsuji Matsuura, Toyokazu Hori, Hiroshi Nogami
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Publication number: 20040264432Abstract: The invention comprises: processing for receiving an OFDM packet having a preamble and the following data transmission symbol, in which packet the subcarrier interval of the preamble is set wider than that of the data transmission symbol; processing for estimating a DC offset occurring at a receiving side by using the received preamble; processing for correcting the DC offset on the received data transmission symbol, according to the estimation result of the DC offset; and processing for demodulating the DC offset corrected data transmission symbol. Thus, it is possible to estimate a DC offset and then correct the DC offset according to the estimated value, in the OFDM packet with no nul symbol defined there.Type: ApplicationFiled: March 26, 2004Publication date: December 30, 2004Applicant: Renesas Technology Corp.Inventors: Toyokazu Hori, Hiroshi Nogami, Toshihito Habuka, Naoto Inokawa, Kazuyuki Takada
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Publication number: 20040264608Abstract: A D.C. offset canceling technique and a gain adjusting technique permitting completion of correction of D.C. offsets and gain adjustment of amplifiers for amplifying reception signals in a relatively short period of time in a radio communication system, such as a wireless LAN, are to be provided. A communication semiconductor integrated circuit (high frequency IC) has a plurality each of low-pass filters and variable gain amplifiers which are alternately connected in multiple stages, and high gain amplifier circuits for amplifying reception signals to a predetermined amplitude level while eliminating unnecessary waves. Offset cancellation values are generated by detecting in advance D.C. offsets of amplifiers for amplifying reception signals according to a set gain, and stored into a memory, and read out of the memory to cancel the D.C. offsets of the amplifiers at the time of starting reception and altering the gain.Type: ApplicationFiled: May 28, 2004Publication date: December 30, 2004Inventors: Toshihito Habuka, Naoto Inokawa, Kiyoharu Ozaki, Tatsuji Matsuura, Koichi Yahagi
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Publication number: 20040022004Abstract: Disclosed here is a wireless LAN system employed for quick and accurate auto gain controlling with no work load to be applied to its baseband processing block. When the wireless LAN system gets ready to receive a signal, the gain control circuit switches between the receiving antennas alternately. The gain control circuit, when receiving a signal over a predetermined receiving sensitivity, sets gain setting value time divisional data according to the level of the received signal measured by the first measurement circuit to roughly control the gain to be set in the LNA and the gain to be set in the two programmable gain amplifiers provided in the front steps of the LPF/PGA circuits. The gain control circuit then cancels the DC offset while the second measurement circuit measures the signal level.Type: ApplicationFiled: July 14, 2003Publication date: February 5, 2004Inventors: Toshihito Habuka, Masaki Noda, Hiroshi Nogami, Toyokazu Hori, Tatsuji Matsuura, Kazuaki Hori, Naoto Inokawa