Patents by Inventor Toshikatsu ITOH
Toshikatsu ITOH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11790867Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: December 7, 2022Date of Patent: October 17, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20230100273Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11551629Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: April 20, 2022Date of Patent: January 10, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20220246105Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11322105Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: August 13, 2021Date of Patent: May 3, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Patent number: 11302718Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interpType: GrantFiled: May 11, 2018Date of Patent: April 12, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Hideki Kitagawa, Teruyuki Ueda, Masahiko Suzuki, Setsuji Nishimiya, Toshikatsu Itoh
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Publication number: 20210390920Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: August 13, 2021Publication date: December 16, 2021Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11189645Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.Type: GrantFiled: March 26, 2018Date of Patent: November 30, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Tetsuo Kikuchi, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20210305280Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.Type: ApplicationFiled: March 26, 2018Publication date: September 30, 2021Inventors: Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Publication number: 20210294138Abstract: A pixel area in the active matrix substrate 100 includes a thin film transistor 101 that has an oxide semiconductor layer 7, an inorganic insulating layer 11 and an organic insulating layer 12 that cover a thin film transistor, a common electrode 15, a dielectric layer 17 that primarily contains silicon nitride, and a pixel electrode 19. The inorganic insulating layer has a multi-layered structure that includes a silicon oxide layer and a silicon nitride layer. A pixel electrode 10 is brought into contact with a drain electrode 9 within a pixel contact hole. The pixel contact hole is configured with a first opening portion, a second opening portion, and a third opening portion that are formed in the inorganic insulating layer 11, the organic insulating layer 12, and the dielectric layer 17, respectively. A flank surface of the first opening portion and a flank surface of the second opening portion are aligned.Type: ApplicationFiled: September 19, 2017Publication date: September 23, 2021Inventors: Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Toshikatsu ITOH, Teruyuki UEDA, Setsuji NISHIMIYA, Kengo HARA
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Patent number: 11107429Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: March 16, 2018Date of Patent: August 31, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Patent number: 11043599Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semiconductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.Type: GrantFiled: March 8, 2018Date of Patent: June 22, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Setsuji Nishimiya, Tohru Daitoh, Masahiko Suzuki, Kengo Hara, Hajime Imai, Toshikatsu Itoh, Hideki Kitagawa, Tetsuo Kikuchi, Teruyuki Ueda
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Patent number: 11038001Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.Type: GrantFiled: March 19, 2018Date of Patent: June 15, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Teruyuki Ueda, Hideki Kitagawa, Tohru Daitoh, Hajime Imai, Masahiko Suzuki, Setsuji Nishimiya, Tetsuo Kikuchi, Toshikatsu Itoh, Kengo Hara
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Patent number: 11037962Abstract: The present invention provides a thin-film transistor array substrate that prevents semiconductor layers of thin-film transistor elements from having step disconnection even when the frame width is reduced. The thin-film transistor array substrate of the present invention includes a thin-film transistor element in a pixel region and a terminal in a terminal region. The thin-film transistor array substrate sequentially includes a support, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer in a cross-sectional view of the pixel region. A region with the insulating layer encompasses a region with the semiconductor layer in a plan view of the pixel region. The thin-film transistor array substrate sequentially includes the support, a lead line extending from the terminal, and the insulating layer in a cross-sectional view of the terminal region.Type: GrantFiled: June 28, 2018Date of Patent: June 15, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tatsuya Kawasaki, Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Toshikatsu Itoh, Hajime Imai, Tohru Daitoh
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Publication number: 20210143184Abstract: The present invention provides a thin-film transistor array substrate that prevents semiconductor layers of thin-film transistor elements from having step disconnection even when the frame width is reduced. The thin-film transistor array substrate of the present invention includes a thin-film transistor element in a pixel region and a terminal in a terminal region. The thin-film transistor array substrate sequentially includes a support, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer in a cross-sectional view of the pixel region. A region with the insulating layer encompasses a region with the semiconductor layer in a plan view of the pixel region. The thin-film transistor array substrate sequentially includes the support, a lead line extending from the terminal, and the insulating layer in a cross-sectional view of the terminal region.Type: ApplicationFiled: June 28, 2018Publication date: May 13, 2021Inventors: Tatsuya KAWASAKI, Hideki KITAGAWA, Yoshihito HARA, Masaki MAEDA, Toshikatsu ITOH, Hajime IMAI, Tohru DAITOH
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Publication number: 20210036158Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semi-conductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.Type: ApplicationFiled: March 8, 2018Publication date: February 4, 2021Inventors: Setsuji NISHIMIYA, Tohru DAITOH, Masahiko SUZUKI, Kengo HARA, Hajime IMAI, Toshikatsu ITOH, Hideki KITAGAWA, Tetsuo KIKUCHI, Teruyuki UEDA
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Patent number: 10825843Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.Type: GrantFiled: October 12, 2017Date of Patent: November 3, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Teruyuki Ueda, Hideki Kitagawa, Tohru Daitoh, Hajime Imai, Masahiko Suzuki, Setsuji Nishimiya, Tetsuo Kikuchi, Toshikatsu Itoh, Kengo Hara
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Patent number: 10818766Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.Type: GrantFiled: March 23, 2018Date of Patent: October 27, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiko Suzuki, Hideki Kitagawa, Tetsuo Kikuchi, Toshikatsu Itoh, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara, Hajime Imai, Tohru Daitoh
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Patent number: 10816865Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).Type: GrantFiled: March 13, 2017Date of Patent: October 27, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Tohru Daitoh, Hajime Imai, Toshikatsu Itoh, Hisao Ochi, Hideki Kitagawa, Masahiko Suzuki, Teruyuki Ueda, Ryosuke Gunji, Kengo Hara, Setsuji Nishimiya
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Patent number: 10756116Abstract: An active matrix substrate includes a gate metal layer including a plurality of gate bus lines, and a thin film transistor arranged in each pixel region, wherein: the thin film transistor includes a gate electrode, an oxide semiconductor layer arranged on the gate electrode with a gate insulating layer interposed therebetween, wherein the gate electrode is formed in the gate metal layer and is electrically connected to a corresponding one of the plurality of gate bus lines, the gate metal layer has a layered structure including a copper alloy layer and a copper layer arranged on the copper alloy layer, wherein the copper alloy layer is of a copper alloy including Cu and at least one additive metal element, wherein the additive metal element includes Al, and an Al content of the copper alloy is 2 at % or more and 8 at % or less.Type: GrantFiled: March 19, 2019Date of Patent: August 25, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Teruyuki Ueda, Yoshihito Hara, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi, Toshikatsu Itoh