Patents by Inventor Toshikazu Abe

Toshikazu Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230222073
    Abstract: An information terminal that uploads IC chip information to a server is provided. The information terminal includes a reading unit that reads information from a recording medium at a first timing based on first information described in setting information, and an upload unit that uploads the information to an external device at a second timing based on second information described in the setting information. the recording medium is an IC chip built in the information terminal or an IC chip accessible from the information terminal. The reading unit reads IC chip information from the IC chip, and the upload unit uploads the IC chip information to the external device.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 13, 2023
    Inventors: YUICHI TODAKA, YUICHIRO FUKUDA, TOSHIKAZU ABE
  • Patent number: 6416586
    Abstract: The present invention has as an object thereof to provide a cleaning method which realizes, in the cleaning process, (1) a reduction in the number of processes, (2) a simplification of the cleaning apparatus, and (3) a reduction in the amount of chemicals and pure water employed, and which has highly superior cleaning effects and does not damage the substrate body, as well as to provide a rinsing method which aids in the hydrogen termination of silicon atoms.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: July 9, 2002
    Assignees: Kabushiki Kaisha Ultraclean Technology Reserach Institute
    Inventors: Tadahiro Ohmi, Toshihiro Il, Kenji Mori, Toshikazu Abe, Hirosi Arakawa, Takahisa Nitta
  • Patent number: 5950222
    Abstract: An EEPROM (1) is set to write mode when a program command to commence rewriting of data in region B in the EEPROM (1) is read out from region A. A CPU (2) then writes data specified by a latch (6) at an address in region B specified by a latch (4). In compliance with an inhibit signal INH, the CPU (2) now disregards the effects of the undefined output from the EEPROM (1) terminal DOUT.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: September 7, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Susumu Yamada, Toru Watanabe, Nobuhiro Arai, Toshikazu Abe