Abstract: A semiconductor apparatus according to the present invention is a semiconductor apparatus on which a plurality of external terminals are disposed. The semiconductor apparatus includes: a first lead portions having die pads, first outer leads and first inner leads; chips; second lead portions having second outer leads and second inner lead; and a resin. On at least one of the first inner leads, the second inner leads and the die pads, a terminal temperature equalizing structure which restricts a heat transfer amount of heat transferred from the chips to predetermined external terminals, and equalizes respective terminal temperatures of a plurality of external terminals is formed. According to the semiconductor apparatus of the present invention, it is possible to prevent specific external terminals from becoming extremely high temperature when the semiconductor apparatus is mounted.

Abstract: A display drive circuit includes: source amplifiers capable of driving source lines of a display panel connected thereto; preamplifiers capable of outputting first gradation voltages; source circuits each including a division of the source amplifiers, provided that the source amplifiers are divided equally; and resistance arrays. Each source circuit is provided with one of the resistance arrays. Each resistance array divides input first gradation voltages to generate second gradation voltages and provides them to the corresponding source circuit. The worsening of the capability of converging of gradation lines for supplying second gradation voltages to the source circuits can be suppressed without providing gradation-voltage-generation circuits even with a display driver IC having an increased long side length, or more than one display driver IC provided.

Abstract: A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.

Abstract: A display drive circuit includes: source amplifiers capable of driving source lines of a display panel connected thereto; preamplifiers capable of outputting first gradation voltages; source circuits each including a division of the source amplifiers, provided that the source amplifiers are divided equally; and resistance arrays. Each source circuit is provided with one of the resistance arrays. Each resistance array divides input first gradation voltages to generate second gradation voltages and provides them to the corresponding source circuit. The worsening of the capability of converging of gradation lines for supplying second gradation voltages to the source circuits can be suppressed without providing gradation-voltage-generation circuits even with a display driver IC having an increased long side length, or more than one display driver IC provided.

Abstract: A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.

Abstract: A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

Abstract: A semiconductor memory device having a plurality of memory arrays in which static memory cells are disposed in a lattice arrangement at intersections of word lines and complementary data lines. The load circuits thereof are characterized as having a varying impedance effected by the combination of a first pair of P-channel MOSFETs disposed between the complementary data lines and a first node supplied with a first supply voltage and kept normally in an ON-state, and a pair of transistors, such as a second pair of P-channel MOSFETs, similarly connected as the first pair of P-channel MOSFETs and which are turned off selectively in accordance with a control signal corresponding to a predetermined selection timing signal in a write-in mode. The semiconductor memory device has a plurality of switching circuits which are coupled between the plurality of complementary data lines and a pair of data read and write lines.

Abstract: In a semiconductor integrated circuit device having memory cell arrays, power source wirings are provided on the memory cell array in parallel with the long side of the memory cell array, thereby strengthening the power source wirings without increasing a chip size and planning reduction in power source impedances.

Abstract: A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

Abstract: A semiconductor memory device having a plurality of memory arrays composed of mutually orthogonal row word lines and complementary column data lines, and static memory cells disposed in a lattice arrangement at the intersections of such word lines and complementary data lines; variable impedance load circuits having first P-channel MOSFETs disposed between the complementary data lines and a first supply voltage and kept normally in an on-state, and also having second P-channel MOSFETs connected in parallel with the first P-channel MOSFETs and cut off selectively in accordance with predetermined selection timing signals in a write mode; a plurality of signal generator circuits provided correspondingly to the memory arrays for forming the selection timing signals in accordance with write control signals and array selection signals, and then feeding the timing signals to the corresponding variable impedance load circuits; and a plurality of signal relay circuits provided correspondingly to a predetermined number